The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2004
Filed:
May. 02, 2002
Dieter Rathei, Graz, AU;
Joerg Wohlfahrt, Yokohama, JP;
Luis G. Andrade, Glen Allen, VA (US);
Robert Petter, Wandiltz, DE;
Thomas S. Taylor, Mechanicsville, VA (US);
Babatunde Ashiru, Chester, VA (US);
Mark E. Luzar, Chester, VA (US);
Michael B. Sommer, Raubling, DE;
Ulrich K. Zimmermann, Mechanicsville, VA (US);
Infineon Technologies Richmond, LP, Sandston, VA (US);
Abstract
A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon. The method comprises calculating a fail region count for each of the tests in the test sequence, calculating the test sequence limited yield loss for each of the wafers, and apportioning the test sequence limited yield loss to selected ones of the test based upon the absolute or cumulative number of fails identified by the tests of the test sequence. In some embodiments, core parametric test data is correlated with the test sequence limited yield and analyzed to determine reparability.