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For the Inventor, By the Inventor

Shoreview, MN, United States of America

Joe M Jeddeloh

LinkedIn
USPTO Granted Patents = 81 

 

Average Co-Inventor Count = 1.3

ph-index = 14

Forward Citations = 842(Granted Patents)


Inventors with similar research interests:


Location History:

  • Minneapolis, MN (US) (1998 - 2002)
  • Shoreview, MN (US) (2008 - 2024)

Company Filing History:

goldMedal73 out of 37,905 
 
Micron Technology Incorporated
 patents
silverMedal8 out of 430 
 
Micron Electronics, Inc.
 patents

Years Active: 1998-2024

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Areas of Expertise:
Memory Devices
Error Management
Flexible Memory Systems
Stacked Memory Architecture
Memory Testing
Data Transfer Management
Embedded Processors
Configurable Bandwidth
Memory Prefetch
Switched Interface
Memory Repair
Memory Power Management
81 patents (USPTO):Explore Patents
1. 11915774 - Memory devices and methods for managing error regions (2024-02-27),
2. 11769534 - Flexible memory system with a controller and a stack of memory (2023-09-26),
3. 11450354 - Flexible memory system with a controller and a stack of memory (2022-09-20),
4. 11145384 - Memory devices and methods for managing error regions (2021-10-12),
5. 11031049 - Flexible memory system with a controller and a stack of memory (2021-06-08),
6. 10878933 - Apparatuses and methods for memory testing and repair (2020-12-29),
7. 10714150 - Flexible memory system with a controller and a stack of memory (2020-07-14),
8. 10445025 - Apparatuses and methods having memory tier structure and recursively searching between tiers for address in a translation table where information is only directly transferred between controllers (2019-10-15),
9. 10430086 - Stacked memory devices, systems, and methods (2019-10-01),
10. 10347356 - Memory devices and methods for managing error regions (2019-07-09),
11. 10297340 - Switched interface stacked-die memory architecture (2019-05-21),
12. 10283172 - Flexible memory system with a controller and a stack of memory (2019-05-07),
13. 10037818 - Switched interface stacked-die memory architecture (2018-07-31),
14. 9990144 - Stacked memory devices, systems, and methods (2018-06-05),
15. 9953724 - Memory devices and methods for managing error regions (2018-04-24),

Title: Joe M Jeddeloh - Innovator in Memory Technology

Introduction

Joe M Jeddeloh is a notable inventor based in Shoreview, MN, whose impressive portfolio includes 81 patents. He has made significant contributions to the field of memory devices and systems, particularly in enhancing their efficiency and reliability.

Latest Patents

Among his latest innovations, Jeddeloh has developed advanced memory devices and methods for managing error regions. These memory devices consist of a stack of memory dies and a logic die, enabling the repartitioning of memory dies for improved management. This technology allows portions of memory to be selectively removed from use without negatively impacting the overall memory device. Additionally, he has created a flexible memory system that features a controller and a stack of memory with several vaults. This innovative setup optimizes functionality by utilizing fewer vault interface blocks than the number of vaults in the system, ultimately enhancing flexibility and efficiency.

Career Highlights

Throughout his career, Joe M Jeddeloh has lent his expertise to leading companies in the tech industry, notably working at Micron Technology Incorporated and Micron Electronics, Inc. His contributions have played a crucial role in advancing memory technology, making his work relevant to both the industry and academia.

Collaborations

Jeddeloh has collaborated with other talented professionals in the field, including noteworthy colleagues such as Paul A LaBerge and Brent Keeth. These partnerships have often led to innovative solutions and have further enriched the landscape of memory technology.

Conclusion

Joe M Jeddeloh’s impact on memory systems through his numerous patents demonstrates his commitment to innovation and technology advancement. His work continues to influence the industry, paving the way for future advancements in memory devices and methods.

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