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For the Inventor, By the Inventor

Sunnyvale, CA, United States of America

Jesse Eugene Chen

This inventor holds 10 USPTO granted patents. Top assignees: Rf Micro Devices, Inc., Cadence Design Systems, Inc., Qualcomm Incorporated. Active years: 1999-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jesse Eugene Chen. Retrieved from https://idiyas.com/inventor/jesse-eugene-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 10

% Patents Active = 80.0

Average Co-Inventor Count = 1.2

ph-index = 7

Forward Citations = 133(Granted Patents)


Company Filing History:

goldMedal5 out of 609 
 
Rf Micro Devices, Inc.
 patents
silverMedal3 out of 2,618 
 
Cadence Design Systems, Inc.
 patents
bronzeMedal1 out of 44,831 
 
Qualcomm Incorporated
 patents
4. 1 out of 834,453 
Other
 patents

Years Active: 1999-2014

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10 patents (USPTO):Explore Patents
1. 8712751 - System and method of verification of analog circuits (2014-04-29),
2. 7567783 - I/Q mismatch calibration of direct conversion transceivers using the OFDM short training sequence (2009-07-28),
3. 7496340 - I/Q mismatch calibration of direct conversion receivers using radio frequency noise (2009-02-24),
4. 7463866 - I/Q mismatch calibration of direct conversion transceivers using the OFDM short training sequence (2008-12-09),
5. 7450919 - I/Q mismatch correction using transmitter leakage and gain modulation (2008-11-11),
6. 6941121 - Method for calibrating a DC offset cancellation level for direct conversion receivers (2005-09-06),
7. 6504885 - System and method for modeling mixed signal RF circuits in a digital signal environment (2003-01-07),
8. 6260176 - Method and system for simulating and making a phase lock loop circuit (2001-07-10),
9. 6181754 - System and method for modeling mixed signal RF circuits in a digital signal environment (2001-01-30),
10. 5987238 - Method and system for simulating and making a phase lock loop circuit (1999-11-16),
Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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