Rf Micro Devices, Inc.

Cadence Design Systems, Inc.

Other

Qualcomm Incorporated

Jesse Eugene Chen

Pengfei Zhang

Steven Mark Thoen

Patrick Vandenameele

Peter Cnudde

Peter Hanson

Alex Zenkin

Dmitri Varsanofiev

In a particular embodiment, a first digital function module is created that represents a first analog circuit and a second digital function module is created that represents a second analog circuit. A first value representing a first analog signal is transmitted from the first digital function module to the second digital function module while concurrently or substantially currently, the second digital function module transmits a second value representing a second analog signal to the first digital function module. In a particular embodiment, the first digital function module is a current signal related to an output of the first analog circuit and the second analog signal from the second digital function module is a voltage signal related to an output of the second analog circuit. The values may be transmitted along a bidirectional analog data bus capable of communicating real floating point numbers.

System and method of verification of analog circuits

A system and method are provided for compensating for an I/Q mismatch of either a direct conversion transmitter or a direct conversion receiver based on known short training symbols of a Short Training Sequence (STS) of packets transmitted according to the IEEE 802.11a or 802.11g standard. To compensate for an I/Q mismatch of a direct conversion transmitter, a packet including the STS is transmitted. Due to the I/Q mismatch of the direct conversion transmitter, the transmitter distorts the packet to provide a distorted packet including a distorted STS. Based on one or more short training symbols of the distorted STS and a known ideal short training symbol, a distortion matrix is determined. Subsequent packets transmitted by the direct conversion transmitter are pre-distorted based on the distortion matrix. Compensation of the I/Q mismatch of a direct conversion receiver may be performed in a similar fashion.

I/Q mismatch calibration of direct conversion transceivers using the OFDM short training sequence

A system and method are provided for calibrating for an I/Q mismatch of a direct conversion receiver based on a random signal having a two-dimensional I versus Q trajectory, such as radio frequency (RF) noise. In general, the random signal is received and downconverted to a quadrature baseband signal having an in-phase component and a quadrature component. The variance of the in-phase component, the variance of the quadrature component, and the covariance of the in-phase component with the quadrature component are computed based on samples of the quadrature baseband signal. A correction matrix used to compensate for the I/Q mismatch of the receiver and/or I/Q mismatch including a gain mismatch and a phase mismatch of the receiver is then computed based on the variance of the in-phase component, the variance of the quadrature component, and the covariance of the in-phase component with the quadrature component.

I/Q mismatch calibration of direct conversion receivers using radio frequency noise

A system and method are provided for compensating for an I/Q mismatch of a receiver in a mobile terminal. In general, the receiver and a transmitter of the mobile terminal are formed on a single substrate. A transmit signal is transmitted via the transmitter. Due to leakage through the substrate, the transmit signal is provided to one or more points in the receiver. One of these points is an input of the amplifier circuitry. A gain of the amplifier circuitry is modulated during reception of the transmit signal such that an amplified signal provided by the amplifier circuitry is offset from the carrier frequency of the transmit signal by a known frequency offset. The amplified signal is downconverted to provide a quadrature output signal. Processing circuitry processes frequency components of the quadrature output signal corresponding to the known frequency offset to determine the I/Q mismatch of the receiver.

I/Q mismatch correction using transmitter leakage and gain modulation

A method for measuring a difference in DC offsets associated with different gain settings in a direct conversion receiver having a variable gain is provided. In a first phase, a set of response parameters that characterize a time-dependent system response to a known change in the DC offset is determined. Each response parameter corresponds to the response measured at a different time after the change. In a second phase, different gain settings are applied to the system and the response is measured at times corresponding to the times associated with each of the response parameters. The response parameters are then used to determine the difference in DC offsets associated with the different gain settings.

Method for calibrating a DC offset cancellation level for direct conversion receivers

A behavioral model for mixed signal RF circuits. The model approximates non-linear filtering effects for base-band (i.e. suppressed carrier) end-to-end systems analysis. The new model, the K-model, is a linear MIMO (multi-input-multi-output) model with output radius corrected by a non-linear SISO (single-input-single output) model and output angle corrected by a non-linear rotation. The SISO model uses a multi-tanh structure to synthesize a non-linear filter. The multi-tanh structure simulates non-linear behavior by gently switching between transfer functions as the base-band input varies. For excursions well into the steady state non-linear region of operation the K-model simulates large-signal base-band transients to within about 10 percent of those simulated with detailed unsuppressed-carrier models.

System and method for modeling mixed signal RF circuits in a digital signal environment

A method of making a phase lock loop circuit is disclosed. The method includes a method of simulating the phase lock loop circuit. The simulation runs on a system for making phase lock loop circuits. The simulation step initializes a reference frequency variable associated with a reference frequency of a phase lock loop circuit. The simulation method also initializes a voltage controlled oscillator (VCO) frequency variable associated with a VCO frequency of the phase lock loop circuit. A phase error is obtained from a frequency error between the reference frequency variable and the VCO frequency variable. The simulation method resets the phase error by a reset phase level when the phase error is approximately the same as a multiple of a reset threshold. When the frequency error changes sign, the phase error is permitted to also change sign. The simulation also determines a loop filter input for the phase lock loop circuit that depends upon the phase error and the frequency error. The simulation method provides a dramatic improvement in simulation time over conventional simulation methods.

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Sunnyvale, CA, United States of America

Jesse Eugene Chen