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For the Inventor, By the Inventor

Bengaluru, India

Jayesh Iyer

This inventor holds 17 USPTO granted patents and 1 published patent application and 2 EPO patents, primarily in Multi-Strand Processor Design. Top assignee: Intel Corporation. Active years: 2013-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jayesh Iyer. Retrieved from https://idiyas.com/inventor/jayesh-iyer

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17 

% Patents Active = 52.9

 

Average Co-Inventor Count = 4.9

ph-index = 3

Forward Citations = 27(Granted Patents)


Location History:

  • Karnataka, IN (2013)
  • Moscow, RU (2018)
  • Santa Clara, CA (US) (2016 - 2019)
  • Bengaluru, IN (2017 - 2021)

Company Filing History:

goldMedal17 out of 56,394 
 
Intel Corporation
 patents

Years Active: 2013-2021

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Areas of Expertise:
Instruction Handling
Memory Allocation
Performance Optimization
Loop Accelerator
Out-Of-Order Processing
Data Cache Control
Voltage Identification
Register Windows
Control Speculation
Hardware Apparatuses
Program Order Reconstruction
Complexity Reduction
17 patents (USPTO):Explore Patents
1. 10884735 - Instruction and logic for predication and implicit destination (2021-01-05),
2. 10346170 - Performing partial register write operations in a processor (2019-07-09),
3. 10324724 - Hardware apparatuses and methods to fuse instructions (2019-06-18),
4. 10241801 - Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator (2019-03-26),
5. 10241794 - Apparatus and methods to support counted loop exits in a multi-strand loop processor (2019-03-26),
6. 10241789 - Method to do control speculation on loads in a high performance strand-based loop accelerator (2019-03-26),
7. 10235171 - Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor (2019-03-19),
8. 10133582 - Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor (2018-11-20),
9. 10095623 - Hardware apparatuses and methods to control access to a multiple bank data cache (2018-10-09),
10. 9904546 - Instruction and logic for predication and implicit destination (2018-02-27),
11. 9858226 - Two wire serial voltage identification protocol (2018-01-02),
12. 9811340 - Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor (2017-11-07),
13. 9645819 - Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor (2017-05-09),
14. 9632790 - Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order (2017-04-25),
15. 9471501 - Hardware apparatuses and methods to control access to a multiple bank data cache (2016-10-18),

Title: The Innovative Mind of Jayesh Iyer

Introduction

Jayesh Iyer is a prominent inventor based in Bengaluru, India, known for his significant contributions to the field of technology. With a remarkable portfolio of 17 patents, he has made a substantial impact in the industry, particularly through his work at Intel Corporation.

Latest Patents

Among his latest patents, Jayesh has developed innovative technologies such as "Instruction and logic for predication and implicit destination." This patent describes a processor that includes a front end to receive an instruction and a core to execute it. The core is designed to execute a base function of the instruction, generate a predicate value based on a comparison of the result, and set this value in a register. Additionally, he has patented "Performing partial register write operations in a processor," which involves logic that performs operations on source operands and writes results to a destination location while maintaining an unmodified portion of the operand.

Career Highlights

Jayesh Iyer's career at Intel Corporation has been marked by his dedication to advancing processor technology. His innovative approaches have not only enhanced the efficiency of processing units but have also paved the way for future developments in the field.

Collaborations

Throughout his career, Jayesh has collaborated with notable colleagues, including Boris A Babayan and Sergey Y Shishlov. These partnerships have fostered a creative environment that encourages the exchange of ideas and the development of groundbreaking technologies.

Conclusion

Jayesh Iyer stands out as a leading inventor whose work continues to shape the future of technology. His contributions through patents and collaborations reflect his commitment to innovation and excellence in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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