The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Dec. 27, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alexander Y. Ostanevich, Moscow, RU;

Jayesh Iyer, Santa Clara, CA (US);

Sergey P. Scherbinin, Obninsk, RU;

Dmitry M. Maslennikov, Moscow, RU;

Denis G. Motin, Moscow, RU;

Alexander V. Ermolovich, Moscow, RU;

Andrey Chudnovets, Moscow, RU;

Sergey A. Rozhkov, San Jose, CA (US);

Boris A. Babayan, Moscow, RU;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/3005 (2013.01); G06F 9/30021 (2013.01); G06F 9/30072 (2013.01); G06F 9/3851 (2013.01);
Abstract

An apparatus includes a first circuit to determine a real program order (RPO) of an eldest undispatched instruction from among a plurality of strands, a second circuit to determine an RPO limit based on a delta value and the RPO of the eldest undispatched instruction, an ordering buffer to store entries for instructions that are waiting to be retired, and a third circuit to execute an orderable instruction from a strand from the plurality of strands to cause an entry for the orderable instruction to be inserted into the ordering buffer in response to a determination that an RPO of the orderable instruction is less than or equal to the RPO limit.


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