Obninsk, Russia

Sergey P Scherbinin

USPTO Granted Patents = 6 

Average Co-Inventor Count = 8.6

ph-index = 1

Forward Citations = 5(Granted Patents)


Location History:

  • Obninsk, RU (2015 - 2019)
  • Kaluga region, RU (2019)

Company Filing History:


Years Active: 2015-2019

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6 patents (USPTO):Explore Patents

Title: Innovations of Sergey P Scherbinin

Introduction

Sergey P Scherbinin is a notable inventor based in Obninsk, Russia. He has made significant contributions to the field of processor architecture, holding a total of 6 patents. His work focuses on enhancing the efficiency and reliability of speculative execution in computing systems.

Latest Patents

One of his latest patents is titled "Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption." This patent discloses methods, apparatus, systems, and articles of manufacture that compile instructions for a vector of instruction pointers (VIP) processor architecture. The method includes identifying a strand with a fork instruction that introduces a first speculative assumption. It also involves initializing a basing value of the strand before executing a first instruction under the first speculative assumption. Furthermore, it determines whether a second instruction under a second speculative assumption modifies a first memory address that is also modified by the first instruction. If the second instruction does not modify the first memory address, it remains unchanged. However, if it does modify the first memory address, the second instruction is adjusted based on the basing value to modify a different memory address.

Another significant patent is the "Method to do control speculation on loads in a high performance strand-based loop accelerator." This apparatus includes a binary translator that hoists a load instruction in a branch of a conditional statement above the statement itself. It inserts a speculation control of load (SCL) instruction in the complementary branch, indicating the real program order (RPO) of the load instruction before it was hoisted. The execution circuit then executes the load instruction and manages its entry in an ordering buffer, ensuring efficient processing.

Career Highlights

Sergey P Scherbinin is currently employed at Intel Corporation, where he continues to innovate in the field of processor technology. His work has been instrumental in advancing the capabilities of modern computing systems.

Collaborations

He has collaborated with notable colleagues such as Dmitry M Maslennikov and Andrey Chudnovets, contributing to various projects that enhance processor performance and reliability.

Conclusion

Sergey P Scherbinin's contributions to processor architecture through his patents and collaborations highlight his role as a key innovator in the field. His work continues to influence advancements in computing technology.

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