The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2017
Filed:
Jun. 15, 2012
Jayesh Iyer, Bangalore, IN;
Nikolay Kosarev, Yoshkar-Ola, IN;
Sergey Shishlov, Moscow, RU;
Alexey Sivtsov, Moscow, RU;
Alexander Butuzov, Moscow, RU;
Boris A. Babayan, Moscow, RU;
Vladimir Penkovski, Folsom, CA (US);
Jayesh Iyer, Bangalore, IN;
Nikolay Kosarev, Yoshkar-Ola, IN;
Sergey Shishlov, Moscow, RU;
Alexey Sivtsov, Moscow, RU;
Alexander Butuzov, Moscow, RU;
Boris A. Babayan, Moscow, RU;
Vladimir Penkovski, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit.