Cupertino, CA, United States of America

Jaya L Jeyaseelan

This inventor holds 26 USPTO granted patents and 5 published patent applications, primarily in Power Management Technologies. Top assignees: Intel Corporation, General Atomics, Inc.. Active years: 2010-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jaya L Jeyaseelan. Retrieved from https://idiyas.com/inventor/jaya-l-jeyaseelan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 26 

% Patents Active = 46.2

Average Co-Inventor Count = 2.5

ph-index = 8

Forward Citations = 171(Granted Patents)


Location History:

  • San Diego, CA (US) (2010 - 2013)
  • Cupertino, CA (US) (2010 - 2015)
  • Campbell, CA (US) (2015 - 2024)

Company Filing History:


Years Active: 2010-2024

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Areas of Expertise:
Power Management
Latency Reporting
Dynamic Data Transfer
Link States
Low Power Devices
Wireless Networks
Universal Serial Bus
Device Activity
Platform Coordination
Input/Output Sub-systems
Roaming Timer
Service Latency
26 patents (USPTO):Explore Patents

Title: **Jaya L Jeyaseelan: Innovator in Power Management Technologies**

Introduction

Jaya L Jeyaseelan is an accomplished inventor based in Cupertino, CA, who holds 26 patents to his name. His work primarily focuses on advancing technologies in memory power management and dynamic input/output data transfer rate scaling, reflecting a commitment to improving the efficiency and performance of computing systems.

Latest Patents

Among his latest patents is a significant innovation titled "Memory Power Management Method and Apparatus." This mechanism enables the effective saving and restoring of locked pages via a hardware accelerator, which operates transparently to the operating system (OS). The process includes the OS placing all Direct Memory Access (DMA) capable devices into low-power states before entering standby. Additionally, it flushes all pageable memory to non-volatile memory (NVM) and creates a comprehensive list of pinned and locked pages in the dynamic random-access memory (DRAM). A power management controller evaluates conditions to intelligently manage power states during standby, ensuring optimal performance with minimal power consumption.

Another notable patent involves "Technologies for Dynamic Input/Output Data Transfer Rate Scaling Based on Power Policy Engine." This patent outlines techniques for regulating I/O power usage by utilizing a power policy engine that observes power consumption, I/O data transfer rates, and temperature fluctuations. Through monitoring, the engine can command adjustments to the data transfer rate of I/O devices, significantly reducing the power expenditure associated with I/O operations.

Career Highlights

Jaya's professional journey includes pivotal roles at esteemed companies such as Intel Corporation and General Atomics, Inc. His contributions to these organizations have not only advanced their technological capabilities but have also positioned them at the forefront of power management innovations in computing.

Collaborations

Throughout his career, Jaya has collaborated with esteemed colleagues, including Barnes Cooper and Robert E. Gough. These partnerships have fostered an environment of innovation and knowledge exchange, further enhancing the technological advancements in their respective fields.

Conclusion

Jaya L Jeyaseelan's extensive portfolio of patents and his commitment to innovation reflect his vital role in advancing power management technologies. His work continues to influence the landscape of computing, ensuring that performance and efficiency go hand in hand in the ever-evolving tech industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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