The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2024
Filed:
Feb. 17, 2021
Intel Corporation, Santa Clara, CA (US);
Nivedha Krishnakumar, San Diego, CA (US);
Virendra Vikramsinh Adsure, Folsom, CA (US);
Jaya Jeyaseelan, Campbell, CA (US);
Nadav Bonen, Ofer Z, IL;
Barnes Cooper, Hillsboro, OR (US);
Toby Opferman, Portland, OR (US);
Vijay Bahirji, Beaverton, OR (US);
Chia-Hung Kuo, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.