The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2015
Filed:
Dec. 28, 2012
Intel Corporation, Santa Clara, CA (US);
Jaya L. Jeyaseelan, Cupertino, CA (US);
Linda Weyhing, Ann Arbor, MI (US);
Rajeev Nalawadi, El Dorado Hills, CA (US);
Barnes Cooper, Tigard, OR (US);
Suraj Varma, Portland, OR (US);
Nevo Idan, Zichron Ya'akov, IL;
David Poisner, Carmichael, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.