The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2019

Filed:

Mar. 08, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jaya L. Jeyaseelan, Campbell, CA (US);

Jim Walsh, Santa Clara, CA (US);

Robert E. Gough, Sherwood, OR (US);

Barnes Cooper, Tigard, OR (US);

Neil W. Songer, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04W 52/02 (2009.01); G06F 13/42 (2006.01); G06F 1/32 (2006.01); H04L 12/26 (2006.01); G06F 1/20 (2006.01);
U.S. Cl.
CPC ...
H04W 52/0225 (2013.01); G06F 1/206 (2013.01); G06F 1/3203 (2013.01); G06F 1/3206 (2013.01); G06F 1/3296 (2013.01); G06F 13/4282 (2013.01); H04L 43/0858 (2013.01); Y02D 10/151 (2018.01); Y02D 70/00 (2018.01); Y02D 70/142 (2018.01); Y02D 70/23 (2018.01);
Abstract

An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.


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