Sunnyvale, CA, United States of America

James J Roman

This inventor holds 24 USPTO granted patents, primarily in Opto-Electronics. Top assignees: Fujitsu Corporation, Adeia Semiconductor Bonding Technologies Inc., Allvia, Inc.. Active years: 1995-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: James J Roman. Retrieved from https://idiyas.com/inventor/james-j-roman

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 79.2

Average Co-Inventor Count = 4.2

ph-index = 16

Forward Citations = 1,587(Granted Patents)


Location History:

  • San Jose, CA (US) (1995)
  • Milpitas, CA (US) (1995 - 1996)
  • Los Altos, CA (US) (1996 - 2000)
  • Sunnyvale, CA (US) (2000 - 2015)

Company Filing History:


Years Active: 1995-2015

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Areas of Expertise:
Opto-Electronic Substrates
Dielectric Trenches
Chemical Mechanical Polishing
Flexible Circuit Structures
Optical Interconnections
Waveguides
Multichip Module
Power Conducting Substrates
Alignment Marks
Non-Destructive Examination
Thin-Film Interconnector
Cleaning Method
24 patents (USPTO):Explore Patents

Title: James J. Roman: Innovator in Dielectric Technologies

Introduction: James J. Roman, based in Sunnyvale, California, is a distinguished inventor with a remarkable portfolio of 24 patents. His innovations primarily focus on dielectric technologies, which have significant implications in the electronics sector.

Latest Patents: Roman's latest patents showcase groundbreaking advancements in dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques. One of his notable contributions involves using a portion of a conductive layer as a capacitor electrode. He developed dielectric trenches within the conductive layer to insulate the capacitor electrode from other conductive paths, ensuring optimal functionality. The capacitor dielectric can be created by anodizing tantalum, while a nickel layer protects the underlying copper from the anodizing solution. This innovative layering allows for a thinner tantalum layer, achieving increased capacitance. Additionally, his method for chemical mechanical polishing has streamlined the process by incorporating photolithographic patterning to enhance the height of the upward protrusions in the layer, making it both faster and potentially more cost-effective.

Career Highlights: Throughout his career, James J. Roman has worked with industry giants such as Fujitsu Corporation and Adeia Semiconductor Bonding Technologies Inc. His efforts have significantly contributed to advancements in semiconductor and capacitor technologies, establishing him as a respected figure in the field.

Collaborations: Roman's notable collaborators include Solomon I. Beilin and Wen-chou Vincent Wang. Together, they have driven research and development initiatives that have led to innovative solutions and technological enhancements in semiconductor manufacturing.

Conclusion: James J. Roman’s contributions to the field of dielectric technologies and his extensive patent portfolio underscore his role as an influential inventor. His ongoing innovations continue to push the boundaries of what is possible in the electronics industry, making a lasting impact on future advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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