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For the Inventor, By the Inventor

Kyunggi-do, South Korea

JaeHyun Lee

USPTO Granted Patents = 10

Average Co-Inventor Count = 3.5

ph-index = 3

Forward Citations = 29(Granted Patents)


Location History:

  • Sungnam, KR (2013 - 2015)
  • Kyungki-do, KR (2014 - 2017)
  • Kyunggi-Do, KR (2015 - 2018)

Company Filing History:

goldMedal10 out of 1,812 
 
Stats Chippac Pte. Ltd.
 patents

Years Active: 2013-2018

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10 patents (USPTO):Explore Patents
1. 10096540 - Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance (2018-10-09),
2. 9679846 - Semiconductor device and method of forming conductive layer over substrate with vents to channel bump material and reduce interconnect voids (2017-06-13),
3. 9460972 - Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection (2016-10-04),
4. 9230933 - Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure (2016-01-05),
5. 9202715 - Integrated circuit packaging system with connection structure and method of manufacture thereof (2015-12-01),
6. 9117812 - Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability (2015-08-25),
7. 9054100 - Semiconductor die and method of forming sloped surface in photoresist layer to enhance flow of underfill material between semiconductor die and substrate (2015-06-09),
8. 8952529 - Semiconductor device with conductive layer over substrate with vents to channel bump material and reduce interconnect voids (2015-02-10),
9. 8642384 - Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability (2014-02-04),
10. 8524538 - Integrated circuit packaging system with film assistance mold and method of manufacture thereof (2013-09-03),

Title: The Innovative Contributions of JaeHyun Lee

Introduction

JaeHyun Lee is a prominent inventor based in Kyunggi-do, South Korea. He has made significant contributions to the field of semiconductor technology, holding a total of 10 patents. His work focuses on enhancing the performance and reliability of semiconductor devices.

Latest Patents

One of JaeHyun Lee's latest patents is a semiconductor device and method of forming dummy pillars between the semiconductor die and substrate for maintaining standoff distance. This invention involves a semiconductor die with an insulation layer and a conductive layer, along with a plurality of conductive and dummy pillars. The dummy pillars are strategically placed to ensure a proper standoff distance between the semiconductor die and the substrate, enhancing device performance.

Another notable patent is the semiconductor device and method of forming a conductive layer over the substrate with vents to channel bump material and reduce interconnect voids. This invention features a semiconductor die with bumps and a first conductive layer that includes vents to facilitate the flow of bump material during the reflow process. This innovation aims to improve the reliability of semiconductor connections.

Career Highlights

JaeHyun Lee is currently employed at Stats Chippac Pte. Ltd., where he continues to develop cutting-edge semiconductor technologies. His expertise in the field has positioned him as a key player in advancing semiconductor device design and manufacturing.

Collaborations

Throughout his career, JaeHyun Lee has collaborated with talented individuals such as KyungHoon Lee and KiYoun Jang. These collaborations have fostered innovation and contributed to the successful development of various semiconductor technologies.

Conclusion

JaeHyun Lee's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor in the industry. His work continues to shape the future of semiconductor devices, ensuring enhanced performance and reliability.

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