Jae-Won Cha

This inventor holds 5 USPTO granted patents and 1 published patent application. Top assignees: Hynix Semiconductor Inc., Skhynix Inc.. Active years: 2009-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jae-Won Cha. Retrieved from https://idiyas.com/inventor/jae-won-cha-hd7iemh6

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 5 (Patent Applications = 1)

% Patents Active = 80.0

Average Co-Inventor Count = 2.5

ph-index = 3

Forward Citations = 13(Granted Patents)

Location History:

Icheon-si, KR (2009)
Seoul, KR (2010 - 2011)
Gyeonggi-do, KR (2014 - 2017)

Company Filing History:

4 out of 6,228

Hynix Semiconductor Inc.

Years Active: 2009-2017

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5 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9613717 - Error correction circuit and semiconductor memory device including the same (2017-04-04),

2. 8812777 - Nonvolatile memory device (2014-08-19),

3. 7948805 - Method of programming a multi level cell (2011-05-24),

4. 7813188 - Non-volatile memory device and a method of programming a multi level cell in the same (2010-10-12),

5. 7623403 - NAND flash memory device and method of operating the same (2009-11-24),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: