Chungcheongbuk-do, South Korea

Jae Cheon Lee

This inventor holds 3 USPTO granted patents and 2 published patent applications. Top assignees: Nepes Co., Ltd., Nepes Laweh Corporation, Other. Active years: 2017-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jae Cheon Lee. Retrieved from https://idiyas.com/inventor/jae-cheon-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 3.8

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:

goldMedal2 out of 27 
 
Nepes Co., Ltd.
 patents
silverMedal2 out of 4 
 
Nepes Laweh Corporation
 patents
bronzeMedal1 out of 834,513 
Other
 patents
where one patent can have more than one assignee

Years Active: 2017-2024

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3 patents (USPTO):Explore Patents

Title: Innovations of Jae Cheon Lee in Semiconductor Technology

Introduction

Jae Cheon Lee is a prominent inventor based in Chungcheongbuk-do, South Korea. He has made significant contributions to the field of semiconductor technology, holding three patents that showcase his innovative approach to semiconductor packaging.

Latest Patents

One of his latest patents is a semiconductor package and method for manufacturing the same. This invention includes a semiconductor package featuring a first semiconductor chip with a bottom surface adjacent to a first active layer and a top surface opposite to the bottom surface. It incorporates a first adhesive layer on the top surface of the first semiconductor chip, a first conductive stud on the bottom surface connected to the first active layer, and a first conductive post outside the chip. The design also includes a redistribution structure beneath the chip, which consists of a redistribution pattern linked to the conductive stud and post, along with a molding layer that encases the entire assembly. Notably, the top surfaces of the molding layer, conductive post, and adhesive layer may be coplanar.

Another patent by Jae Cheon Lee also focuses on a semiconductor package and method for manufacturing the same. This invention features a semiconductor chip with a first surface adjacent to an active layer and a second surface opposite to it. It includes a conductive stud on the first surface connected to the active layer, an adhesive layer on the second surface, and a conductive post outside the chip. The design incorporates a first redistribution structure on the first surface and a second redistribution structure on the second surface, along with a molding layer that surrounds the semiconductor chip and its components.

Career Highlights

Jae Cheon Lee has worked with notable companies such as Nepes Co., Ltd. and Nepes Laweh Corporation. His experience in these organizations has contributed to his expertise in semiconductor technology and innovation.

Collaborations

Throughout his career, Jae Cheon Lee has collaborated with talented individuals, including Byung Cheol Kim and Yong Tae Kwon. These collaborations have likely enhanced his work and contributed to the development of his patents.

Conclusion

Jae Cheon Lee's contributions to semiconductor technology through his innovative patents demonstrate his expertise and commitment to advancing the field. His work continues to influence the industry and pave the way for future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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