The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2024

Filed:

Nov. 11, 2021
Applicants:

Nepes Co., Ltd., Chungcheongbuk-do, KR;

Nepes Laweh Corporation, Chungcheongbuk-do, KR;

Inventors:

Byung Cheol Kim, Incheon, KR;

Yong Tae Kwon, Chungcheongbuk-do, KR;

Hyo Gi Jo, Chungcheongbuk-do, KR;

Dong Hoon Oh, Chungcheongbuk-do, KR;

Jae Cheon Lee, Chungcheongbuk-do, KR;

Hyung Jin Shin, Chungcheongbuk-do, KR;

Mary Maye Melgo Galimba, Cavite, PH;

Assignees:

NEPES CO., LTD., Chungcheongbuk-do, KR;

NEPES LAWEH CORPORATION, Chungcheongbuk-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 24/16 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/32 (2013.01); H01L 25/16 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/32238 (2013.01);
Abstract

Provided is a semiconductor package including a first semiconductor chip having a bottom surface adjacent to a first active layer and an top surface opposite to the bottom surface; a first adhesive layer disposed on the top surface of the first semiconductor chip; a first conductive stud disposed on the bottom surface of the first semiconductor chip and electrically connected to the first active layer; a first conductive post disposed outside the first semiconductor chip; a redistribution structure disposed under the first semiconductor chip and including a redistribution pattern connected to the first conductive stud and the first conductive post and a redistribution insulation layer surrounding the redistribution pattern; and a molding layer surrounding the first semiconductor chip, the first adhesive layer, the first conductive stud, and the first conductive post on the redistribution structure. Also, a top surface of the molding layer, a top surface of the conductive post, and a top surface of the first adhesive layer may be coplanar.


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