Ian D Miller

This inventor holds 22 USPTO granted patents, primarily in Dataflow Circuit Design. Top assignees: Xilinx, Inc., Tsi Telsys, Inc.. Active years: 2000-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ian D Miller. Retrieved from https://idiyas.com/inventor/ian-d-miller

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 22

% Patents Active = 100.0

Average Co-Inventor Count = 3.7

ph-index = 11

Forward Citations = 912(Granted Patents)

Location History:

Columbia, MD (US) (2000 - 2002)
Raleigh, NC (US) (2013)
Charlotte, NC (US) (2003 - 2016)

Company Filing History:

Years Active: 2000-2016

Loading Chart...

Areas of Expertise:

Content-Based Caching

Dataflow Applications

Integrated Circuit

Asynchronous Communication

Hardware Implementation

High Level Languages

FPGA Programming

Resource Estimation

Event Notification

Architecture Mapping

Multi-Staged Processing

Software Constructs

22 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9411744 - Content-based caching in a managed runtime computing environment (2016-08-09),

2. 9117046 - Method of generating data for estimating resource requirements for a circuit design (2015-08-25),

3. 8595391 - Automatic queue sizing for dataflow applications (2013-11-26),

4. 8572432 - Method and apparatus for processing an event notification in a concurrent processing system (2013-10-29),

5. 8402164 - Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit (2013-03-19),

6. 8146040 - Method of evaluating an architecture for an integrated circuit device (2012-03-27),

7. 8020139 - Method and apparatus for implementing a dataflow circuit model using application-specific memory implementations (2011-09-13),

8. 8001510 - Automated method of architecture mapping selection from constrained high level language description via element characterization (2011-08-16),

9. 7979835 - Method of estimating resource requirements for a circuit design (2011-07-12),

10. 7822886 - Dataflow control for application with timing parameters (2010-10-26),

11. 7509619 - Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages (2009-03-24),

12. 7222314 - Generation of a hardware interface for a software procedure (2007-05-22),

13. 7143388 - Method of transforming software language constructs to functional hardware equivalents (2006-11-28),

14. 7111274 - Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations (2006-09-19),

15. 7086047 - Determining hardware generated by high level language compilation through loop optimizations (2006-08-01),

Ian D Miller is a resident of Charlotte, NC (US) who has established himself as an accomplished inventor with 18 patents to his name. Among his most notable recent patents is a method of content-based caching in a managed runtime computing environment. This computer-implemented method involves loading source data and comparing the content with a plurality of cache entries to output a transformation for the source data. Another recent invention from Mr. Miller is a method of generating data for estimating resource requirements for a circuit design. This method involves identifying intermediate circuit modules, elaborating each module according to an associated parameter set, generating an estimate of resources for each module, and storing the estimates of resources.

Ian D Miller has worked in various companies throughout his career, including Xilinx, Inc. and TSI Telsys, Inc. At these companies, he has worked alongside other notable professionals in his field, such as Jorn W Janneck and Jonathan C Harris. Mr. Miller's impressive array of patents and his collaborations with other experienced innovators make him a valuable contributor to any team or project.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]