Xilinx, Inc.

Tsi Telsys, Inc.

Ian D Miller

Jonathan C Harris

Jorn W Janneck

David Bruce Parlour

Stephen G Edwards

Donald J Davis

Andreas Benno Kollegger

James E Jensen

Toby D Bennett

Christopher R S Schanck

Paul R Schumacher

Pradip Jha

Conor C Wu

Stephen Andrew Neuendorffer

Yung-Sheng Yu

Christopher Robert Sunderland Schanck

A computer-implemented method of caching data in a managed runtime computing environment can include loading source data and comparing content of the source data with at least one of a plurality of cache entries. Each cache entry can include a representation of previously received source data and a transformation of the previously received source data. A transformation for the source data from a cache entry can be selected or a transformation for the source data can be generated according to the comparison. The transformation for the source data can be output.

Content-based caching in a managed runtime computing environment

A method of generating data for estimating resource requirements for a circuit design is disclosed. The method comprises identifying a plurality of intermediate circuit modules of netlists for circuit designs; elaborating each intermediate circuit module of the plurality of intermediate circuit modules according to an associated plurality of parameter sets; generating an estimate of resources for each intermediate circuit module and parameter set of the associated plurality of parameter sets; and storing the estimates of resources for the intermediate circuit modules.

Method of generating data for estimating resource requirements for a circuit design

Automatic queue sizing for data flow applications for an integrated circuit is described. Queue sizes for queues of a dataflow network are initialized to a set of first sizes for running as distributed actors without having to have centralized control. If it is determined there is a deadlock, causes for the dataflow network being deadlocked are analyzed with a controller coupled thereto to select a first actor thereof. The first actor of the dataflow network is selected as being in a stalled write phase state. Queue size is incremented for at least one queue of the queues to unlock the first actor from the stalled write phase state. The running, the determining, the analyzing, and the incrementing are iteratively repeated to provide a second set of sizes for the queue sizes sufficient to reduce likelihood of deadlock of the data flow network.

Automatic queue sizing for dataflow applications

In one embodiment, a concurrent processing system is disclosed. For example, in one embodiment of the present invention, a concurrent processing system, comprises a first processing element comprising a first monitor module, a second processing element in communication with the first processing element, the second processing element comprising a second monitor module, and a first system monitor for receiving a notification from at least one of: the first processing element, or the second processing element, wherein the notification indicates an event detected by one of the first monitor module, or the second monitor module.

Method and apparatus for processing an event notification in a concurrent processing system

An asynchronous communication network in an integrated circuit is described. The asynchronous communication network comprises a plurality of circuit elements enabling the transmission of tokens, each circuit element having a component interface comprising: a routing network coupled to a first adjacent circuit element of the plurality of circuit elements; and a control circuit coupled to the routing network, the control circuit having a first input coupled to receive a first command requesting a detection of a token received at a second input of the control circuit, and a first acknowledgement output coupling a first acknowledgement signal indicating whether the first command is received at the first input. Methods of enabling asynchronous communication in an integrated circuit are also disclosed.

Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit

A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the intermediate format to a dataflow program defined in terms of the predefined library of primitives; and generating an implementation profile comprising information related to an implementation of the original dataflow program in an integrated circuit having the predetermined architecture. A method of evaluating an architecture for an integrated circuit device is also disclosed.

Method of evaluating an architecture for an integrated circuit device

Method, apparatus, and computer readable medium for implementing a circuit model in an integrated circuit are described. In some examples, the circuit model includes a communication channel between actors. Data portions of at least one data object passed between the actors over the communication channel are identified. An implementation is generated for the circuit model in which data portions are assigned to either local queue storage of the communication channel or centralized shared storage of the communication channel based on levels of access thereof by the actors.

Method and apparatus for implementing a dataflow circuit model using application-specific memory implementations

Disclosure is made of approaches for mapping an electronic design specification to an implementation. In one approach, quality metrics are associated with functional units of the design, and the functional units are mapped to respective initial implementations. For each functional unit a respective quality indicator is determined based on the mapping. The quality indicator specifies a degree to which the functional unit achieves the associated quality metric. At least one of the functional units is selected for remapping based on the quality indicator of that functional unit or the quality indicator of another functional unit. An alternative implementation to the initial implementation is selected for each selected functional unit to improve the quality indicator. The selected functional unit is remapped to the selected alternative implementation.

Automated method of architecture mapping selection from constrained high level language description via element characterization

A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.

Method of estimating resource requirements for a circuit design

Dataflow control for an application with timing parameters, including interfacing temporal and non-temporal domains, is described. The domains receive input data to a first dataflow network block, which is processed for untimed output of first tokens. The first tokens are obtained by a memory interface for timed writing of data portions of the first tokens to data storage and for timed reading of the data portions therefrom. Sending of the data portions read to a first queue of a first controller block is untimed, and the data portions are output by the first controller block with physical timing parameters. Second tokens are generated by the first controller block responsive to the physical timing parameters. The second tokens are fed back to a second queue of the first dataflow network block to control rate of generation of the first tokens by the first dataflow network block.

Dataflow control for application with timing parameters

A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.

Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages

Generation of a hardware interface specification for a software procedure. In one embodiment, an HDL description is generated for a first memory, at least one first state machine, a second memory, at least one second state machine, and an activation signal. The first memory stores input data corresponding to a plurality of data values consumed by the software procedure. The first state machine receives the input data and stores the input data in the first memory, and at least one of the at least one first state machines receives a plurality of the data values. The second memory stores output data corresponding to at least one data value produced by the software procedure. The second state machine reads the output data from the second memory and sends the output data.

Generation of a hardware interface for a software procedure

A method of designing an integrated circuit using a general purpose programming language can include identifying a number of instances of each class allocated in a programmatic design implemented using the general purpose programming language and modeling the global memory of the programmatic design. A data flow between the modeled global memory and instructions of the programmatic design which access object fields can be determined and access to the modeled global memory can be scheduled. The programmatic design can be translated into a hardware description of the integrated circuit using the modeled global memory, the data flow, and the scheduled memory access.

Method of transforming software language constructs to functional hardware equivalents

A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model () and identifying data input to each component specified in the language independent model to determine a latency for each component (). The components of the language independent model can be annotated for generation of control signals such that each component is activated when both control and valid data arrive at the component (). Each component also can be annotated with an output latency derived from a latency of a control signal for the component and a latency determined from execution of the component itself ().

Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations

A method of processing a program written in a general purpose programming language to determine a hardware representation of the program can include generating a language independent model of the program written in a general purpose programming language () and identifying a loop construct within the language independent model (). A determination can be made as to whether the loop construct is bounded (). If so, a loop processing technique can be selected for unrolling the loop construct according to stored user preferences). The loop construct can be replicated in the language independent model as specified by the selected loop processing technique ().

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Charlotte, NC, United States of America

Ian D Miller