The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2006

Filed:

Dec. 04, 2002
Applicants:

Stephen G. Edwards, Woodbine, MD (US);

Donald J. Davis, Ellicott City, MD (US);

Jonathan C. Harris, Ellicott City, MD (US);

Andreas B. Kollegger, Baltimore, MD (US);

Ian D. Miller, Charlotte, NC (US);

Christopher R. S. Schanck, Marriottsville, MD (US);

Yung-sheng Yu, Columbia, MD (US);

Inventors:

Stephen G. Edwards, Woodbine, MD (US);

Donald J. Davis, Ellicott City, MD (US);

Jonathan C. Harris, Ellicott City, MD (US);

Andreas B. Kollegger, Baltimore, MD (US);

Ian D. Miller, Charlotte, NC (US);

Christopher R. S. Schanck, Marriottsville, MD (US);

Yung-Sheng Yu, Columbia, MD (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model () and identifying data input to each component specified in the language independent model to determine a latency for each component (). The components of the language independent model can be annotated for generation of control signals such that each component is activated when both control and valid data arrive at the component (). Each component also can be annotated with an output latency derived from a latency of a control signal for the component and a latency determined from execution of the component itself ().


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