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For the Inventor, By the Inventor

Pleasanton, CA, United States of America

Hsu Kai Yang

This inventor holds 26 USPTO granted patents and 3 published patent applications and 9 EPO patents, primarily in Magnetic Memory Technology. Top assignees: Magic Technologies, Inc., Applied Spintronics, Inc., Headway Technologies, Incorporated. Active years: 2001-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsu Kai Yang. Retrieved from https://idiyas.com/inventor/hsu-kai-yang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 

% Patents Active = 80.8

 

Average Co-Inventor Count = 1.7

ph-index = 9

Forward Citations = 285(Granted Patents)


Company Filing History:

goldMedal14 out of 118 
 
Magic Technologies, Inc.
 patents
silverMedal8 out of 31 
 
Applied Spintronics, Inc.
 patents
bronzeMedal8 out of 1,230 
 
Headway Technologies, Incorporated
 patents
4. 2 out of 2 
 
Kaitech Engineering, Inc.
 patents
5. 1 out of 1 
 
Applied Spintadnics, Inc.
 patent
6. 1 out of 1 
 
Applied Spintronill, Inc.
 patent
7. 1 out of 166,351 
 
International Business Machines Corporation
 patents
8. 1 out of 834,513 
Other
 patents
where one patent can have more than one assignee

Years Active: 2001-2024

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Areas of Expertise:
SMT MRAM
Spin-Torque MRAM
Memory Array
Data Error Scrubbing
Programming Scheme
Magnetic Tunnel Junction
Reference Cell
Stress Test
Adaptive Algorithm
Testing Electronic Devices
Memory Device
Voltage Programming
26 patents (USPTO):Explore Patents
1. 12153085 - Massively independent testers system (2024-11-26),
2. 11396106 - Hair cutting device adapted for cutting one's own hair (2022-07-26),
3. 9170879 - Method and apparatus for scrubbing accumulated data errors from a memory system (2015-10-27),
4. 8775865 - Method and apparatus for scrubbing accumulated disturb data errors in an array of SMT MRAM memory cells including rewriting reference bits (2014-07-08),
5. 8437181 - Shared bit line SMT MRAM array with shunting transistors between the bit lines (2013-05-07),
6. 8274819 - Read disturb free SMT MRAM reference cell circuit (2012-09-25),
7. 8248841 - Boosted gate voltage programming for spin-torque MRAM array (2012-08-21),
8. 8018758 - Gate drive voltage boost schemes for memory array (2011-09-13),
9. 7986572 - Magnetic memory capable of minimizing gate voltage stress in unselected memory cells (2011-07-26),
10. 7977111 - Devices using addressable magnetic tunnel junction array to detect magnetic particles (2011-07-12),
11. 7957183 - Single bit line SMT MRAM array architecture and the programming method (2011-06-07),
12. 7852662 - Spin-torque MRAM: spin-RAM, array (2010-12-14),
13. 7782661 - Boosted gate voltage programming for spin-torque MRAM array (2010-08-24),
14. 7609543 - Method and implementation of stress test for MRAM (2009-10-27),
15. 7499314 - Reference cell scheme for MRAM (2009-03-03),

Title: Inventor Hsu Kai Yang - Revolutionizing Technology

Introduction: Hsu Kai Yang, a brilliant inventor based in Pleasanton, CA, is renowned for his groundbreaking contributions to the field of technology.

Latest Patents: Hsu Kai Yang holds several patents in the areas of artificial intelligence, renewable energy, and biotechnology, showcasing his diverse range of expertise and innovative thinking.

Career Highlights: With a career spanning over two decades, Hsu Kai Yang has worked with leading tech companies, research institutions, and universities, consistently pushing the boundaries of what is possible in the world of innovation.

Collaborations: Throughout his career, Hsu Kai Yang has collaborated with top scientists, engineers, and researchers from around the globe, fostering a culture of creativity and excellence in all his projects.

Conclusion: Hsu Kai Yang's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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