Magic Technologies, Inc.

Headway Technologies, Incorporated

Applied Spintronics, Inc.

Kaitech Engineering, Inc.

Other

International Business Machines Corporation

Applied Spintronill, Inc.

Applied Spintadnics, Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Applied Spintronics Technology, Inc.

Hsu Kai Yang

Po-Kang Wang

Xizeng Shi

Bruce Yee Yang

Xi Zeng Shi

Yutaka Nakamura

Po Kang Wang

Pokang Wang

Lejan Pu

John Debrosse

Perng-Fei Yuh

Jerin Tzenjie Luangrath

Luke Tzenmin Luangrath

Yin Rong

Apparatuses, systems, methods, and computer program products for massively independent testers systems are disclosed. An apparatus includes a controller, a substrate, a device interface board, multiple tester modules mounted on the substrate, and/or one or more interface buses. One or more components for tester modules are mounted on a device interface board. Tester modules are configured to perform both independent functional and parametric tests. One or more interface buses are in communication with a controller, multiple tester modules, and/or a device interface board to provide one or more of power and a communication link.

Massively independent testers system

A hair cutting device adapted for cutting one's own hair comprises a comb piece having teeth with smooth comb edges near open ends and sharp cutting edges near closed ends, a moving cutting arm with sharp cutting teeth in contact and rough alignment with the sharp cutting edges of the comb piece, capable of reciprocating sideways back and forth and cutting hair in conjunction with the sharp cutting edges of the comb piece, and a hair guard in close proximity along their lengths. The hair guard can be lowered to expose the sharp cutting edges of the comb piece and moving cutting arm to cut hair or raised above the sharp cutting edges to work as a comb.

Hair cutting device adapted for cutting one's own hair

A data scrubbing apparatus corrects disturb data errors occurring in an array of memory cells such as SMT MRAM cells. The data scrubbing apparatus receives an error indication that an error has occurred during a read operation of a grouping of memory cells within the array of memory cells. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data. Based on a scrub threshold value, the data scrubbing apparatus writes the corrected data back after a specific number of errors. The data scrubbing apparatus may further suspend writing back during a writing of data. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

Method and apparatus for scrubbing accumulated data errors from a memory system

A data scrubbing apparatus corrects disturb errors occurring in a memory cell array, such as SMT MRAM cells. The data scrubbing apparatus activates scrubbing of the data and associated error correction bits based on a number of errors corrected, at a power up of the memory cell array, or a programmed time interval. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data, the associated error correction bits, and reference bits. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

Method and apparatus for scrubbing accumulated disturb data errors in an array of SMT MRAM memory cells including rewriting reference bits

An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

Shared bit line SMT MRAM array with shunting transistors between the bit lines

An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect.

Read disturb free SMT MRAM reference cell circuit

A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical '1' to the MTJ element of a selected spin-torque MRAM cell.

Boosted gate voltage programming for spin-torque MRAM array

This invention describes a circuit and method to limit the stress caused by gate voltages required to write a one or zero in magnetic memory elements using the Giant magneto-resistive effect, such as Phase Change RAM and Spin Moment Transfer MRAM, sometimes referred to as Spin Torque Transfer MRAM, which require high programming currents. The circuit and method selects one cell at a time for writing a one or a zero, different voltages to write a one or a zero, and a precharge circuit to limit the stress on non selected cells.

Gate drive voltage boost schemes for memory array

Magnetic memory elements such as Phase Change RAM and Spin Moment Transfer MRAM require high programming currents. These high programming currents require high gate to source/drain voltages for the cell transistors controlling these programming currents, which can degrade the reliability of these cell transistors. This invention describes a circuit and method to write information into individual memory cells while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written. The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array. During the write operation the voltage is raised for the word line of only one row of the array. The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row.

Magnetic memory capable of minimizing gate voltage stress in unselected memory cells

A magnetic sensor for identifying small superparamagnetic particles bonded to a substrate contains a regular orthogonal array of MTJ cells formed beneath that substrate. A magnetic field imposed on the particle, perpendicular to the substrate, induces a magnetic field that has a component within the MTJ cells that is along the plane of the MTJ free layer. If that free layer has a low switching threshold, the induced field of the particle will create resistance changes in a group of MTJ cells that lie beneath it. These resistance changes will be distributed in a characteristic formation or signature that will indicate the presence of the particle. If the particle's field is insufficient to produce the free layer switching, then a biasing field can be added in the direction of the hard axis and the combination of this field and the induced field allows the presence of the particle to be determined.

Devices using addressable magnetic tunnel junction array to detect magnetic particles

An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal. Out-of-phase switching devices are connected to the source lines for selectively transferring the out-of-phase signal to the at least one source lines. Column select transistors are connected to the single bit lines for transferring an in-phase data signal to a selected column of the SMT MRAM cells. A precharge circuit selectively charges or discharges the single bit lines. Ground switching devices selectively connect to the source lines to a ground reference voltage source. A method for programming a selected SMT MRAM cell within a provided SMT MRAM device is described.

Single bit line SMT MRAM array architecture and the programming method

A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.

Spin-torque MRAM: spin-RAM, array

Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.

Method and implementation of stress test for MRAM

An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.

Growing community of inventors

Pleasanton, CA, United States of America

Hsu Kai Yang