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Hsinchu, Taiwan

Hsing-Chien Huang

This inventor holds 6 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 1999-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsing-Chien Huang. Retrieved from https://idiyas.com/inventor/hsing-chien-huang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6

% Patents Active = 66.7

Average Co-Inventor Count = 3.0

ph-index = 4

Forward Citations = 54(Granted Patents)


Location History:

  • Tapei Hsien, TW (1999)
  • Taipei Hsien, TW (1999)
  • Hsinchu, TW (2004 - 2010)

Company Filing History:

goldMedal6 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 1999-2010

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6 patents (USPTO):Explore Patents
1. 7802209 - Method for reducing timing libraries for intra-die model in statistical static timing analysis (2010-09-21),
2. 7155696 - Interconnection routing method (2006-12-26),
3. 7103862 - Method to design and verify an integrated circuit device with multiple power domains (2006-09-05),
4. 6789248 - Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization (2004-09-07),
5. 5914892 - Structure and method of array multiplication (1999-06-22),
6. 5867453 - Self-setup non-overlap clock generator (1999-02-02),

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Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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