The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2006
Filed:
Mar. 23, 2004
Nai-yin Sung, Hsin Chu, TW;
Hsing-chien Huang, Hsin Chu, TW;
Jan-hun Tsai, HsinChu, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A new method to design and verify a multi-power integrated circuit device is achieved. A multi-power gate-level netlist is provided. This multi-power gate-level netlist includes multi-power net information. This multi-power gate-level netlist is translated to thereby create a non-multi-power gate-level netlist. This translating comprises removing the multi-power net information. Circuit cells are then placed and routed to create a physical view of the multi-power integrated circuit device. This placing and routing step uses the non-multi-power gate-level netlist. Text labels for the multi-power net information are attached to the physical view. The physical view and the multi-power gate-level netlist are compared to verify the correctness of the physical view and to complete the design and verification of the multi-power integrated circuit device.