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For the Inventor, By the Inventor

Taoyuan, Taiwan

Hsin-Yun Hsu

This inventor holds 14 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2020-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsin-Yun Hsu. Retrieved from https://idiyas.com/inventor/hsin-yun-hsu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 4

Forward Citations = 23(Granted Patents)


Company Filing History:

goldMedal14 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2020-2025

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14 patents (USPTO):Explore Patents
1. 12354876 - Gate structure passivating species drive-in method and structure formed thereby (2025-07-08),
2. 12278288 - Fin field-effect transistor device having hybrid work function layer stack (2025-04-14),
3. 12051753 - Fin field-effect transistor device having hybrid work function layer stack (2024-07-30),
4. 12021145 - Fin field-effect transistor device having hybrid work function layer stack (2024-06-25),
5. 11830742 - Selective capping processes and structures formed thereby (2023-11-28),
6. 11710638 - Gate structure passivating species drive-in method and structure formed thereby (2023-07-25),
7. 11380793 - Fin field-effect transistor device having hybrid work function layer stack (2022-07-05),
8. 11380542 - Selective capping processes and structures formed thereby (2022-07-05),
9. 11201227 - Gate structure with barrier layer and method for forming the same (2021-12-14),
10. 11145747 - FinFET structure (2021-10-12),
11. 11024505 - Gate structure passivating species drive-in method and structure formed thereby (2021-06-01),
12. 10854459 - Gate structure passivating species drive-in method and structure formed thereby (2020-12-01),
13. 10790142 - Selective capping processes and structures formed thereby (2020-09-29),
14. 10770288 - Selective capping processes and structures formed thereby (2020-09-08),

Title: **Hsin-Yun Hsu: Pioneering Innovations in Semiconductor Technology**

Introduction

Hsin-Yun Hsu is a distinguished inventor based in Taoyuan, Taiwan, known for his significant contributions to the semiconductor industry. With a portfolio of 12 patents, Hsu continues to push the boundaries of innovation, particularly in the development of advanced semiconductor devices that enhance performance and efficiency.

Latest Patents

One of Hsu's most notable recent inventions is the "Fin field-effect transistor device having hybrid work function layer stack." This groundbreaking patent details a semiconductor device designed with multiple fins that protrude above a substrate. The innovative structure includes a unique gate dielectric layer and a layered work function system, using different materials to optimize performance. This invention reflects his commitment to advancing semiconductor technologies, ensuring improved functionality in electronic devices.

Career Highlights

Hsin-Yun Hsu is currently associated with the Taiwan Semiconductor Manufacturing Company Limited (TSMC), a leader in the global semiconductor industry. His work at TSMC has positioned him at the forefront of technology development, where he continues to innovate and contribute to the creation of next-generation semiconductor solutions.

Collaborations

Throughout his career, Hsu has collaborated with fellow innovators such as Hsiao-Kuan Wei and Chih-Chien Chi. These collaborations have enabled Hsu to enhance his research insights and develop innovative solutions that significantly impact the semiconductor field.

Conclusion

Hsin-Yun Hsu stands out as a prominent figure in the world of semiconductor innovation. With his numerous patents and collaborative efforts, he exemplifies the spirit of innovation crucial to advancing technology. As the industry evolves, Hsu’s work continues to be instrumental in shaping the future of semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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