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For the Inventor, By the Inventor

Taipei, Taiwan

Hsin-Chin Jiang

This inventor holds 26 USPTO granted patents, primarily in Electrostatic Discharge Protection. Top assignees: Industrial Technology Research Institute, Amazing Microelectronic Corporation, Other. Active years: 2002-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsin-Chin Jiang. Retrieved from https://idiyas.com/inventor/hsin-chin-jiang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26

% Patents Active = 100.0

Average Co-Inventor Count = 2.9

ph-index = 9

Forward Citations = 262(Granted Patents)


Location History:

  • Chutung, Hsinchu, TW (2007 - 2009)
  • Hsinchu, TW (2003 - 2010)
  • Shinyi Chiu, Taipei, TW (2007 - 2010)
  • Taipei, TW (2002 - 2012)
  • Taipei County, TW (2012)

Company Filing History:

goldMedal15 out of 9,303 
 
Industrial Technology Research Institute
 patents
silverMedal4 out of 93 
 
Amazing Microelectronic Corporation
 patents
bronzeMedal6 out of 834,453 
Other
 patents
where one patent can have more than one assignee

Years Active: 2002-2012

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Areas of Expertise:
Electrostatic Discharge
Mixed-Voltage Interface
Transient Voltage Detection
Latch-Up Protection
Protection Circuit
Silicon Controlled Rectifier
Circuit Design
Charge-Device Model
High ESD Stress
Low-Capacitance Bonding Pad
Bipolar Junction Transistors
Programmable ADC
26 patents (USPTO):Explore Patents
1. RE43215 - ESD protection design with turn-on restraining method and structures (2012-02-27),
2. 8116049 - Transient voltage detection circuit (2012-02-14),
3. 8067952 - System-level ESD detection circuit (2011-11-29),
4. 7989923 - Bi-directional transient voltage suppression device and forming method thereof (2011-08-02),
5. 7974053 - ESD protection circuit for differential I/O pair (2011-07-05),
6. 7675724 - Electrostatic discharge protection device for mixed voltage interface (2010-03-09),
7. 7663853 - On-chip latch-up protection circuit (2010-02-16),
8. 7554159 - Electrostatic discharge protection device and method of manufacturing the same (2009-06-30),
9. 7394630 - Electrostatic discharge protection device for mixed voltage interface (2008-07-01),
10. 7304827 - ESD protection circuits for mixed-voltage buffers (2007-12-04),
11. 7253999 - On-chip latch-up protection circuit (2007-08-07),
12. 7253453 - Charge-device model electrostatic discharge protection using active device for CMOS circuits (2007-08-07),
13. 7092227 - Electrostatic discharge protection circuit with active device (2006-08-15),
14. 6882009 - Electrostatic discharge protection device and method of manufacturing the same (2005-04-19),
15. 6838908 - Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits (2005-01-04),

Title: Inventor Hsin-Chin Jiang: Revolutionizing Technology from Taipei

Introduction: Hsin-Chin Jiang, a visionary inventor hailing from Taipei, Taiwan, has been at the forefront of technological advancements in the region.

Latest Patents: Jiang's latest patents focus on cutting-edge innovations in the fields of artificial intelligence, renewable energy, and biotechnology, showcasing his versatility and forward-thinking approach.

Career Highlights: With a career spanning over two decades, Jiang has made significant contributions to the tech industry, with several groundbreaking inventions that have reshaped the way we interact with technology on a daily basis.

Collaborations: Throughout his career, Jiang has collaborated with leading research institutions, universities, and tech companies to further his inventions and bring them to the market, solidifying his reputation as a pioneer in the field.

Conclusion: Hsin-Chin Jiang's relentless pursuit of innovation and his passion for pushing the boundaries of technology have cemented his status as a prominent figure in the world of inventions, with his impact reverberating far beyond the borders of Taipei, Taiwan.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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