The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2005
Filed:
Mar. 28, 2003
Ming-dou Ker, Hsinchu, TW;
Che-hao Chuang, Hsinchu, TW;
Kuo-chung Lee, Hsinchu, TW;
Hsin-chin Jiang, Hsinchu, TW;
Ming-Dou Ker, Hsinchu, TW;
Che-Hao Chuang, Hsinchu, TW;
Kuo-Chung Lee, Hsinchu, TW;
Hsin-Chin Jiang, Hsinchu, TW;
Industrial Technology Research Institute, Hsinchu, TW;
Abstract
A mixed-voltage I/O buffer circuit that prevents leakages through a driver stage PMOS transistor is provided. The buffer circuit has a first part that prevents leakage through a parasitic diode of the transistor and a second part that prevents leakage through the transistor when the transistor is turned on by a signal on a bonding pad having a voltage level higher than a power supply voltage of the buffer circuit. The buffer circuit provides biases approximately equal to the high voltage signal to a gate and a substrate terminal of the PMOS transistor when the bonding pad has the high voltage signal thereon, and provides a bias approximately equal to the power supply voltage of the buffer circuit to the gate and substrate of the PMOS transistor when the bonding pad has a low voltage signal thereon.