The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2010

Filed:

May. 02, 2008
Applicants:

Ming-dou Ker, Hsinchu, TW;

Kuo-chun Hsu, Hsinchu, TW;

Hsin-chin Jiang, Hsinchu, TW;

Inventors:

Ming-Dou Ker, Hsinchu, TW;

Kuo-Chun Hsu, Hsinchu, TW;

Hsin-Chin Jiang, Hsinchu, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.


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