The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2007

Filed:

May. 02, 2003
Applicants:

Zi-ping Chen, Chutung, Hsinchu, TW;

Ming-dao Ker, Chutung, Hsinchu, TW;

Hsin-chin Jiang, Chutung, Hsinchu, TW;

Inventors:

Zi-Ping Chen, Chutung, Hsinchu, TW;

Ming-Dao Ker, Chutung, Hsinchu, TW;

Hsin-Chin Jiang, Chutung, Hsinchu, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An ESD protection circuit that protects a mixed-voltage input/output (I/O) buffer circuit in an integrated circuit is provided. The ESD protection circuit includes an ESD discharging circuit coupled to the I/O pad and ESD detection circuit coupled to the discharging circuit providing a means for detecting an ESD and triggering the discharging circuit to conduct the ESD to ground. The ESD discharging circuit comprises stacked NMOS transistors or a field oxide device (FOD). The protection circuit can also be used in an ESD protection circuit for a high-voltage-tolerant input pad or to protect multiple input pads and/or multiple I/O pads in an integrated circuit.


Find Patent Forward Citations

Chen, Zi-Ping. (2007). Esd protection circuits for mixed-voltage buffers (U.S. Patent No. 7304827). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7304827

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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