Ome, Japan

Hiroshi Ashihara

This inventor holds 9 USPTO granted patents. Top assignees: Renesas Technology Corp., Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.. Active years: 2004-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiroshi Ashihara. Retrieved from https://idiyas.com/inventor/hiroshi-ashihara-wpsftrkp

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 33.3

Average Co-Inventor Count = 5.2

ph-index = 4

Forward Citations = 50(Granted Patents)


Location History:

  • Ome, JP (2004 - 2010)
  • Hachioji, JP (2011)

Company Filing History:


Years Active: 2004-2011

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9 patents (USPTO):Explore Patents

Title: Hiroshi Ashihara: Innovator in Semiconductor Technology

Introduction

Hiroshi Ashihara is a prominent inventor based in Ome, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 9 patents. His innovative work has paved the way for advancements in semiconductor devices, particularly in the manufacturing processes that enhance performance and efficiency.

Latest Patents

One of Ashihara's latest patents is a method of manufacturing a semiconductor device having a MIM capacitor. In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer are made thicker than those of other metallic interconnect layers. The film thickness of the upper barrier film of the lower electrode is controlled to be 110 nm or more, preferably 160 nm or more. This innovation prevents a decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film, allowing for higher deposition temperatures and resulting in a semiconductor device with improved performance and capacitance.

Another significant patent involves a semiconductor integrated circuit device and a method of manufacturing the same. In this process, an interconnect trench and a contact hole are formed in an interlayer insulating film over a first-level interconnect on a semiconductor substrate. A barrier film is formed inside the trench and contact hole, with its thickness increasing from the center of the bottom toward the sidewalls. A copper film is then deposited over the barrier film, and a second-level interconnect and connector portion are formed through polishing. This method ensures that the current pathway is dispersed, preventing electron concentration and enhancing device reliability.

Career Highlights

Hiroshi Ashihara has worked with notable companies in the semiconductor industry, including Renesas Technology Corporation and Hitachi, Ltd. His experience in these organizations has contributed to his expertise and innovative capabilities in semiconductor technology.

Collaborations

Throughout his career, Ashihara has collaborated with talented individuals such as Tatsuyuki Saito and Kensuke Ishikawa. These collaborations have fostered a creative environment that has led to groundbreaking advancements in semiconductor manufacturing.

Conclusion

Hiroshi Ashihara's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the field. His work continues to influence the development of high-performance semiconductor

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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