Renesas Technology Corp.

Hitachi, Ltd.

Other

Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Hiroshi Ashihara

Tatsuyuki Saito

Kensuke Ishikawa

Toshio Saito

Masanori Miyauchi

Hidenori Suzuki

Yasuko Yoshida

Toshinori Imai

Tsuyoshi Fujiwara

Hideaki Tsugane

Ken Okutani

Uitsu Tanaka

Yoshihiro Kawasaki

Masaaki Yoshida

Toshio Saitoh

Akira Ootaguro

Tomohiro Shiraishi

In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

Method of manufacturing semiconductor device having MIM capacitor

In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.

Semiconductor integrated circuit device and a method of manufacturing the same

Semiconductor integrated circuit device with a connective portion for multilevel interconnection

In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.

Semiconductor integrated circuit device with a metallization structure

Method of manufacturing a semiconductor integrated circuit device including a hole formed in an insulating film and a first conductive film formed over a bottom region and sidewalls of the hole

A semiconductor device has a first insulating film deposited over a semiconductor substrate, an interconnect opening portion formed in the first insulating film, an interconnect disposed in the interconnect opening portion, and a second insulating film formed over the first insulating film and the interconnect. The interconnect has a first conductor film, a second conductor film formed via the first conductor film and comprised of one of titanium silicon nitride, tantalum silicon nitride, tantalum nitride and titanium nitride, a third conductor film formed via the first and second conductor films and comprised of a material having good adhesion with copper; and a fourth conductor film formed via the first, second and third conductor conductor film having a copper as a main component. Thus, it is possible to improve adhesion between a conductor film composed mainly of copper and another conductor film having a copper-diffusion barrier function in the interconnect.

Semiconductor device

Method of manufacturing a multilayer metallization structure with non-directional sputtering method

Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer and than a bonding pad, is formed within an aperture formed in silicon oxide films and is interposed between the wiring line and the bonding pad.

Method for manufacturing semiconductor integrated circuit devices using a conductive layer to prevent peeling between a bonding pad and an underlying insulating film

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Ome, Japan

Hiroshi Ashihara