Manassas, VA, United States of America

Harish N Kotecha

This inventor holds 22 USPTO granted patents, primarily in Semiconductor Devices. Top assignees: International Business Machines Corporation, United States of America as Represented by the Secretary of the Air Force. Active years: 1978-1992.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Harish N Kotecha. Retrieved from https://idiyas.com/inventor/harish-n-kotecha

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 14

Forward Citations = 718(Granted Patents)


Location History:

  • Essex Junction, VT (US) (1982 - 1983)
  • Manassas, VA (US) (1978 - 1992)

Company Filing History:


Years Active: 1978-1992

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Areas of Expertise:
High Circuit Density
Dopant Concentration
ROM Data State
Resistive Gate FET
Photoresist Lift-Off
Integrated Dynamic RAM
Non-Volatile RAM
Electrically Alterable Memory
Dual Implant Drain Extension
MOSFET Device
Quaternary FET
IGFET Fabrication
22 patents (USPTO):Explore Patents

Harish N Kotecha: Innovator in Semiconductor Technology

Introduction

Harish N Kotecha, located in Manassas, VA, is a prominent inventor recognized for his significant contributions to semiconductor technology. With a portfolio boasting 22 patents, Kotecha has developed groundbreaking methods that enhance circuit fabrication and dopant concentration in semiconductors. His innovations have had a lasting impact on the field and have been crucial for advancements in electronic devices.

Latest Patents

Among Kotecha's notable patents is the "Method for Fabricating High Circuit Density, Self-Aligned Metal Lines". This method details the fabrication of patterned conductive lines that are perfectly aligned with underlying contact windows. The process involves forming a layer of a photosensitive material over a dielectric layer, which is then expertly processed to ensure a precise structure. Various reactive ion etch steps facilitate the selective removal of dielectric material while protecting the conductive line areas, ultimately allowing for improved circuits.

Another significant patent by Kotecha is the "Method for Providing Increased Dopant Concentration in Selected Regions". This method focuses on enhancing dopant concentration in semiconductor regions by strategically implanting dopants within the transition region. The process includes forming a thin insulating layer on a semiconductor substrate, depositing an anti-oxidant layer, and utilizing various etching and ion-implanting techniques to achieve the desired semiconductor properties.

Career Highlights

Kotecha has worked for reputable organizations such as IBM and The United States of America as represented by the Secretary of the Air. His experience in these institutions has allowed him to collaborate on numerous advanced projects, pushing the boundaries of semiconductor technology.

Collaborations

Throughout his career, Kotecha has collaborated with other esteemed professionals in the field, including Kenneth E Beilstein, Jr. and Francis W Wiedman, III. These partnerships have played a vital role in the development and refinement of his innovative techniques and methods.

Conclusion

Harish N Kotecha is a distinguished inventor whose work continues to pave the way for advancements in semiconductor technology. With 22 patents to his name and a career marked by significant contributions, Kotecha's impact on the industry is undeniable. His methods for high circuit density fabrication and enhanced dopant concentration represent crucial innovations that will benefit the field for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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