International Business Machines Corporation

United States of America As Represented by the Secretary of the Air Force

Harish N Kotecha

Claude Louis Bertin

Kenneth E Beilstein, Jr

Francisco H De La Moneda

Francis W Wiedman, Iii

Wendell P Noble

Howard L Kalter

Lawrence G Heller

David Stanasolovich

Parsotam Trikam Patel

Donelli J DiMaria

Edward C Fredericks

Donald A Soderman

Harry J Jones

Hans A Protschka

Jeffrey R Barber

Francisco H DeLaMoneda

Arthur R Edenfeld

Al M Bracco

Jake Theisen

David D Meyer

Dave Stanasolovich

A method is disclosed for fabricating patterned conductive lines which are self-aligned with underlying contacts windows. A layer of a photosensitive material such photoresist is formed over a dielectric layer. The photoresist layer is processed to have fully developed areas corresponding to contact windows, partially developed areas corresponding to the patterned conductive lines and undeveloped areas which correspond to field areas where the entire dielectric layer is maintained. The dielectric layer is preferably a compound dielectric layer to reduce interlevel shorts. Through the use of selective etch steps, the compound dielectric layers aid in the formation of the patterned conductive line and contact window structure. A series of reactive ion etch (RIE) steps are performed. The first RIE step, highly selective to dielectric material as compared to photoresist, etches the fully developed areas at least partially through the dielectric thickness. In the second RIE step, the photoresist which protected dielectric in the conductive line areas is removed. The third RIE step is also selective to dielectric material as compared to photoresist and etches the dielectric to form channels where the conductive lines are formed, and completes the etching in the contact window areas. The remaining resist is then removed. The channels and contacts are overfilled with a deposition of a conductive material. This conductive material is then planarized by either a RIE process or a chemical-mechanical polishing step.

Method for fabricating high circuit density, self-aligned metal linens

A method for providing increased dopant concentration in selected regions of semiconductors by providing field implant dopant in the transition region located below the 'bird's beak' region and between the field and active regions of a semiconductor. The method comprises the steps of: forming a thin insulating layer on the surface of a semiconductor substrate; depositing a thin anti-oxidant layer on the insulating layer; depositing a layer of photoresist on the anti-oxidant layer; selectively etching the anti-oxidant layer; ion-implanting the field region of the semiconductor substrate; providing spacers on the sides of the anti-oxidant layer; and oxidizing the semiconductor substrate.

Method for providing increased dopant concentration in selected regions

A read/write memory cell is disclosed in which multiple ROM data states can be stored. Independent sensing of the resistance values of each of two resistors accounts for the storage of multiple ROM data states. The resistors are encompassed in a pair of cross-coupled resistive gate devices forming branch circuits, thereby allowing each branch circuit to control the conduction of current in the other branch circuit. This allows for read/write data storage in flip-flop-like fashion. In addition, since resistive gate devices are used, the ROM data may be programmed during the later stages of manufacturing.

Multiple ROM data state, read/write memory cell

A resistor personalized memory cell consisting of a resistive gate field effect transistor. One end of the gate electrode is connected to the memory cell access line, the other end to one of its source or drain regions. The source or drain region not connected to the gate electrode is connected to the memory cell bit line. Memory cell personalization is accomplished by selecting the resistance of the resistive gate. Memory cell data is read by detecting the current flow through the cell, the magnitude of the current flow being proportional to the gate resistance.

Resistor personalized memory device using a resistive gate fet

A method making self-aligned semiconductors utilizing two resist masking steps to form a device; making one of the masks insoluable with respect to the other so that when a first part of the device is formed by a first mask, and a second part of the device is formed by the second masks, the parts are self-aligned when the first resist is dissolved.

Photoresist lift-off process for fabricating semiconductor devices

The process sequence is disclosed which applies a polycrystalline silicon gate material, then applies a chemical vapor deposition oxide over all surfaces, forming an effective sidewall on each of the polycrystalline silicon gate structures. An ion implantation step is then carried out to implant source and drain regions whose proximate edges are not aligned with the edges of the polycrystalline silicon gate material itself, due to the masking effect of the sidewall portion of the chemical vapor deposition oxide layer. Thereafter, the chemical vapor deposition oxide sidewall material is selectively removed for those FET device locations where an active FET device is desired to be formed in the operation of personalizing the read only storage or PLA product. Those locations are then ion implanted for source and drain extensions which are then self-aligned with the respective edges of the respective polycrystalline silicon gate electrodes. The process enables a significantly reduced turnaround time for personalizing read only memory arrays which contain FET memory devices having a shorter channel length, higher breakdown voltage characteristic, an almost zero channel hot electron effect, and a lower gate-to-source/drain diffusion overlap capacitance than most other FET read only memory devices.

Method of making ROM/PLA semiconductor device by late stage

A combined read-only storage (ROS) and read/write random access memory (RAM) integrated circuit memory cell is disclosed. In a first cell embodiment, a ROS FET device and a RAM FET device are connected in common to a bit sensing line connected to a sense amplifier which senses if the ROS FET device has discharged the bit sensing line indicating that a gate is present on the ROS FET device. A write driver circuit is also connected to the bit sensing line, for providing current through the RAM FET device to the charge storage element for writing a one or a zero therein. In a second cell embodiment, a combined two-bit read-only storage and one-bit read/write random access memory integrated circuit cell is disclosed. The bit sensing line is shared by two ROS FET devices and one RAM FET device. In a third cell embodiment of the invention, a single binary bit is stored for read-only storage and a single binary bit is stored for read/write random access memory storage. The charge storage element shares a common node with the ROS FET device and the RAM FET device and the sense amplifier is connected to the opposite side of the RAM FET device.

Integrated dynamic RAM and ROS

A two carrier dual injector semiconductor apparatus utilizing a pair of injector gates for simultaneously injecting holes and electrons into a series stack of insulator layers. The stacked insulator layers which may be arranged in a MIM or MIS configuration have injecting layers near opposing metal gates for injecting either electrons as holes into the insulator layers depending upon the polarity of the applied bias voltage. The apparatus is capable of high-current low-voltage carrier injection while maintaining a stable trapped spaced charge within the stack of insulator layers.

Two carrier dual injector apparatus

This invention provides improved non-volatile semiconductor memories which include a volatile latch circuit having a data node and first and second cross-coupled transistors, at least one of the transistors has first and second control gates, a floating gate and an enhanced conduction insulator or dual electron injector structure disposed between the first control gate and the floating gate. The second control gate is connected to the storage node. A control voltage source is connected to the first control gate for transferring charge between the enhanced conduction insulator or dual electron injector structure and the data node.

Non-volatile static RAM cell with enhanced conduction insulators

This invention provides improved non-volatile semiconductor memories which include a volatile circuit coupled to a non-volatile device having a floating gate and first and second control gates capacitively coupled to the floating gate with a charge injector structure disposed between the floating gate and one of the two control gates. The volatile circuit may be a dynamic one-device cell or a static cell such as a conventional flip-flop or latch cell.

Non-volatile RAM cell with enhanced conduction insulators

An electrically alterable double dense memory is provided which includes a field effect transistor having first and second spaced apart diffusion regions of a first conductivity defining a channel region at the surface of a semiconductor substrate having a second conductivity. First and second floating gates are disposed over the first and second diffusion regions, respectively, and each extends over an end of the channel region. First and second dual charge injector structures or enhanced conduction insulators are disposed between the first and second floating gates and a common control gate of the transistor. A word line is connected to the control gate and first and second bit lines are connected to the first and second diffusion regions. By applying appropriate pulses to the word and bit lines, a selected floating gate can be charged to alter the conductivity of the end of the channel region associated with the selected floating gate and then discharged at will. In this manner binary digits of information are stored in each of the two floating gates and altered as desired. By applying appropriate voltages to the control gate and to one of the first and second diffusion regions, the stored information or charge condition of the floating gate associated with the other of the first and second diffusion regions can be determined.

Electrically alterable double dense memory

This invention provides improved non-volatile semiconductor memories which include a one device dynamic volatile memory circuit having a storage capacitor with a plate and a storage node coupled to a non-volatile device having a floating gate, a control gate and a voltage divider having first and second serially-connected capacitors, with the floating gate being disposed at the common point between the first and second capacitors. The plate of the storage capacitor is connected to a reference voltage source. The control gate is preferably capacitively coupled to the floating gate through the first capacitor which includesa dual charge or electron injector structure. The capacitance of the first capacitor has a value substantially less than that of the second capacitor.

Non-volatile dynamic RAM cell

The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A first thin N-type region is implanted at a first concentration in a portion of the P-type channel region of an FET device adjacent to the drain diffusion. A second region is implanted with N-type dopant at a second concentration less than the first concentration, adjacent to and continuous with the first implanted region. The N-type concentration in the second region is just sufficient to compensate for the P-type background doping in the channel region. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

Process for making a dual implanted drain extension for bucket brigade

A memory system is provided for charging and discharging small cells each of which has only three terminals with a charge injector controlled by a low single polarity voltage. Each of the cells includes a transistor having a current carrying electrode and a floating gate, with a control gate arranged so that a first capacitor is serially connected with a second capacitor between the current carrying electrode and the control gate, with one of the capacitors having a substantially larger capacitance than that of the other capacitor and with the other capacitor including a charge injector. The common point between the first and second capacitors is connected to the floating gate. The charge injector may include a single graded or stepped composition region or two such regions disposed near opposite faces or plates of the other capacitor, or more particularly the injector may include silicon rich regions near one or both faces of a layer of silicon dioxide.

Three terminal electrically erasable programmable read only memory

An improved memory system is provided for charging and discharging a conductive plate such as a floating gate of a field effect transistor with a charge injector controlled by a low single polarity voltage pulse. In the system of the invention, the conductive plate may be a floating gate of a field effect transistor which also includes first and second or dual control gates. A single or double graded band gap layer, such as a silicon rich layer of silicon dioxide is disposed only between the floating gate and the first control gate forming a capacitor having a given capacitance with a larger capacitor disposed between the second control gate and the floating gate. These cells or transistors may be used in an array for storing for long periods of time, on the order of 10 years or more, binary digits of information representing a 0 or a 1 depending upon whether a charge is stored on the floating gate. When using these cells in a memory array, information may be written into or erased from each of the cells individually or a blanket erase may be employed for the entire or a selected section of the array. To write and to erase a cell, a low single polarity voltage is employed. Several embodiments of the invention are disclosed including one embodiment wherein the dual gates are located on one side of the floating gate, a second embodiment which uses a diffusion in a semiconductor substrate as one of the control gates and a third embodiment wherein one of the control gates is disposed on one side of, or above, the floating gate and the other control gate is disposed on the other side of, or below, the floating gate near the surface of the channel region of the transistor.

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Manassas, VA, United States of America

Harish N Kotecha