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For the Inventor, By the Inventor

Tokyo, Japan

Hajime Matsuzawa

This inventor holds 8 USPTO granted patents and 1 published patent application. Top assignee: Nec Corporation. Active years: 2000-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hajime Matsuzawa. Retrieved from https://idiyas.com/inventor/hajime-matsuzawa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 8 

% Patents Active = 62.5

Average Co-Inventor Count = 1.3

ph-index = 4

Forward Citations = 105(Granted Patents)


Company Filing History:

goldMedal8 out of 36,718 
 
Nec Corporation
 patents

Years Active: 2000-2008

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8 patents (USPTO):Explore Patents
1. 7386407 - Semiconductor device test method using an evaluation LSI (2008-06-10),
2. 7295027 - Semiconductor device socket and semiconductor device connecting method using anisotropic conductive sheet (2007-11-13),
3. 6891386 - Semiconductor device socket and semiconductor device connecting method using anisotropic conductive sheet (2005-05-10),
4. 6515497 - Air pump operated test fixture and method for testing a circuit board (2003-02-04),
5. 6472724 - Electronic device structure capable of preventing malfunction caused by electromagnetic wave coming from outside (2002-10-29),
6. 6343365 - Large-scale integrated circuit and method for testing a board of same (2002-01-29),
7. 6310780 - Surface mount assembly for electronic components (2001-10-30),
8. 6047394 - Circuit for easily testing a logic circuit having a number of (2000-04-04),

Title: Hajime Matsuzawa: Innovator in Semiconductor Technology

Introduction

Hajime Matsuzawa is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 8 patents. His innovative work has paved the way for advancements in semiconductor device testing and connection methods.

Latest Patents

Matsuzawa's latest patents include a semiconductor device test method utilizing an evaluation LSI. This evaluation LSI features a noise generation circuit that produces a controlled amount of noise from outside the LSI. It also includes a delay measurement circuit that measures the signal delay of a delay circuit influenced by this noise. By determining the relationship between the amount of noise and the signal delay, the device-under-test (DUT) LSI can estimate the noise based on the evaluated signal delay.

Another notable patent is for a semiconductor device socket and connecting method using an anisotropic conductive sheet. This socket includes a support member for a substrate, an anisotropic conductive sheet for electric connection, and a heater that heats the conductive sheet. The heating process expands the sheet before the semiconductor device is installed, ensuring optimal performance.

Career Highlights

Matsuzawa is currently employed at NEC Corporation, where he continues to innovate in semiconductor technologies. His work has been instrumental in enhancing the efficiency and reliability of semiconductor devices.

Collaborations

Throughout his career, Matsuzawa has collaborated with notable colleagues, including Koetsu Tamura and Hiroo Ito. These partnerships have fostered a creative environment that has led to groundbreaking advancements in their field.

Conclusion

Hajime Matsuzawa's contributions to semiconductor technology through his patents and collaborations highlight his role as a leading inventor. His innovative methods and devices continue to influence the industry, showcasing the importance of creativity and research in technological advancement.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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