The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2008
Filed:
Mar. 13, 2006
Yukihiko Tanikawa, Tokyo, JP;
Hajime Matsuzawa, Tokyo, JP;
Yukihiko Tanikawa, Tokyo, JP;
Hajime Matsuzawa, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
An evaluation LSI includes a noise generation circuit generating a controlled amount of noise controlled from outside of the LSI, and a delay measurement circuit measuring a signal delay of a delay circuit influenced by the noise. The relationship between the amount of noise and the signal delay is determined. A device-under-test (DUT) LSI includes a functional circuit and a delay circuit having a signal delay influenced by the operation of the functional test. By evaluating the signal delay of the delay circuit in the DUT LSI, the amount of noise therein is estimated based on the determined relationship.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile