Circuit for easily testing a logic circuit having a number of

Abstract

A scan path circuit is for use in testing a logic package designed in accordance with scan path fashion. The logic package comprises a logic circuit and a plurality of scan paths. The logic circuit has first through N-th input/output pins, where N represents a positive integer which is greater than one. The scan paths are connected in serial to one another and are connected to the logic circuit. The scan path circuit comprises first through N-th memory sections which are connected in serial to one another and which are connected to the first through the N-th input/output pins, respectively. Each of the memory sections comprises a first memory circuit and a second memory circuit. The first memory circuit of an n-th memory section supplies test input to an n-th input/output pin in a shifting mode, where n is a variable between one and N. The first memory circuit of the n-th memory section takes test output from the logic circuit through the n-th input/output pin in a normal mode. The second memory circuit of the n-th memory section holds test input in the shifting mode to prevent the test input from varying to a varied input.