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For the Inventor, By the Inventor

Caserta, Italy

Giuseppe D'Eliseo

This inventor holds 38 USPTO granted patents and 13 published patent applications and 2 EPO patents, primarily in NAND Memory Management. Top assignees: Micron Technology Incorporated, Lodestar Licensing Group LLC. Active years: 2015-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Giuseppe D'Eliseo. Retrieved from https://idiyas.com/inventor/giuseppe-d-eliseo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 38 

% Patents Active = 94.7

 

Average Co-Inventor Count = 5.1

ph-index = 4

Forward Citations = 45(Granted Patents)


Location History:

  • Caserta, IT (2015 - 2024)
  • Avezzano, IT (2024)

Company Filing History:

goldMedal34 out of 39,222 
 
Micron Technology Incorporated
 patents
silverMedal1 out of 218 
 
Lodestar Licensing Group LLC
 patents
where one patent can have more than one assignee

Years Active: 2015-2026

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Areas of Expertise:
Data Block Refresh
Adaptive Block Mapping
NAND Data Placement
Logical-to-Physical Mapping
Memory Device Recovery
Cache Read Switching
Garbage Collection
Power Loss Mitigation
Sequential Data Reading
NAND Operation Latency
Hybrid Caching Scheme
Corrupted Storage Recovery
38 patents (USPTO):Explore Patents
1. 12724566 - Direct logical-to-physical address mapping for sequential physical addresses (2026-09-01),
2. 12705001 - Integrated pivot table in a logical-to-physical mapping (2026-08-11),
3. 12461660 - Data block refresh during read access (2025-11-04),
4. 12353770 - Adaptive block mapping (2025-07-08),
5. 12321594 - Clustered parity for NAND data placement schema (2025-06-03),
6. 12293101 - Data relocation operation techniques (2025-05-06),
7. 12277979 - NAND data placement schema (2025-04-14),
8. 12216943 - Integrated pivot table in a logical-to-physical mapping (2025-02-04),
9. 12183407 - Setting switching for single-level cells (2024-12-31),
10. 12073113 - Direct logical-to-physical address mapping for sequential physical addresses (2024-08-27),
11. 12056046 - Corrupted storage portion recovery in a memory device (2024-08-06),
12. 11955189 - NAND data placement schema (2024-04-09),
13. 11941300 - Integrated pivot table in a logical-to-physical mapping (2024-03-26),
14. 11922069 - Adaptive block mapping (2024-03-05),
15. 11922053 - NAND logical-to-physical table region tracking (2024-03-05),

Title: The Innovative Mind of Giuseppe D'Eliseo

Introduction: Giuseppe D'Eliseo, a talented inventor hailing from Caserta, Italy, is renowned for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Giuseppe D'Eliseo holds several patents in various technological domains, showcasing his versatility and creativity in inventing cutting-edge solutions for modern challenges.

Career Highlights: Throughout his illustrious career, Giuseppe D'Eliseo has consistently pushed the boundaries of innovation, with his inventions revolutionizing industries such as robotics, renewable energy, and healthcare.

Collaborations: Giuseppe D'Eliseo has collaborated with leading research institutions, universities, and tech companies worldwide, fostering a culture of innovation and knowledge exchange that has led to remarkable advancements in science and technology.

Conclusion: Giuseppe D'Eliseo's passion for innovation, coupled with his relentless pursuit of excellence, has solidified his reputation as a visionary inventor whose impact will be felt for generations to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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