The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2024
Filed:
May. 04, 2022
Micron Technology, Inc., Boise, ID (US);
Umberto Siciliani, Rubano, IT;
Tao Liu, San Jose, CA (US);
Ting Luo, Santa Clara, CA (US);
Dionisio Minopoli, Frattamaggiore, IT;
Giuseppe D'Eliseo, Caserta, IT;
Giuseppe Ferrari, Naples, IT;
Walter Di Francesco, Avezzano, IT;
Antonino Pollio, Vico Equense, IT;
Luigi Esposito, Piano di Sorrento, IT;
Anna Scalesse, Arzano, IT;
Allison J. Olson, Boise, ID (US);
Anna Chiara Siviero, Albignasego, IT;
Micron Technology, Inc., Boise, ID (US);
Abstract
Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.