Gerald L Cadloni

This inventor holds 45 USPTO granted patents and 5 published patent applications and 3 EPO patents, primarily in Memory Subsystems. Top assignee: Micron Technology Incorporated. Active years: 2013-2025.

USPTO Granted Patents = 45 (Patent Applications = 5)

% Patents Active = 93.3

EPO Patents = 3 (Patent Applications = 3)

Average Co-Inventor Count = 2.6

ph-index = 6

Forward Citations = 97(Granted Patents)

Company Filing History:

45 out of 39,149

Micron Technology Incorporated

patents

Years Active: 2013-2025

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Areas of Expertise:

Dynamic Calibration

Error Recovery

Background Scan

Threshold Voltage

Memory Components

Block Management

Quality Metrics

Real Time Analysis

Temperature Readings

Multi-Level Systems

Non-Volatile Memory

LDPC Calibration

45 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12265447 - Memory sub-system with dynamic calibration using component-based function(s) (2025-04-01),

2. 11953980 - Memory sub-system with dynamic calibration using component-based function(s) (2024-04-09),

3. 11791004 - Threshold voltage offset bin selection based on die family in memory devices (2023-10-17),

4. 11715530 - Offset memory component automatic calibration (autocal) error recovery for a memory sub-system (2023-08-01),

5. 11714709 - Enhanced block management for a memory subsystem (2023-08-01),

6. 11714580 - Dynamic background scan optimization in a memory sub-system (2023-08-01),

7. 11709732 - Mitigating read disturb effects in memory devices (2023-07-25),

8. 11705215 - Memory sub-system with background scan and histogram statistics (2023-07-18),

9. 11687408 - Memory sub-system codeword quality metrics streaming (2023-06-27),

10. 11669398 - Memory components with ordered sweep error recovery (2023-06-06),

11. 11545227 - Threshold voltage offset bin selection based on die family in memory devices (2023-01-03),

12. 11526393 - Memory sub-system with dynamic calibration using component-based function(s) (2022-12-13),

13. 11392328 - Dynamic background scan optimization in a memory sub-system (2022-07-19),

14. 11379304 - Mitigating read disturb effects in memory devices (2022-07-05),

15. 11361833 - Offset memory component automatic calibration (autocal) error recovery for a memory subsystem (2022-06-14),

Title: Unveiling the Inventive Journey of Gerald L Cadloni

Introduction: Meet Gerald L Cadloni, a visionary inventor based in Longmont, CO (US), with an impressive portfolio of 44 patents to his name. His innovative spirit and dedication to technological advancement have propelled him to the forefront of the industry.

Latest Patents: Among his recent groundbreaking inventions is the "Memory sub-system with dynamic calibration using component-based function(s)" - a cutting-edge apparatus designed to dynamically calibrate read voltages for optimized performance. Additionally, Gerald's "Threshold voltage offset bin selection based on die family in memory devices" demonstrates his expertise in memory technology and efficiency in read operations.

Career Highlights: Gerald L Cadloni is a valuable asset to Micron Technology Incorporated, where he channels his passion for innovation into tangible solutions. His contributions have significantly impacted the technology sector, paving the way for new advancements in memory systems.

Collaborations: In his professional journey, Gerald has collaborated with esteemed coworkers such as Bruce A Liikanen and Larry Joseph Koudele. Together, they have synergized their expertise to drive innovation and excellence in the field of technology.

Conclusion: Gerald L Cadloni's remarkable achievements in the realm of inventions and patents underscore his prolific career as an inventor. His unwavering commitment to pushing boundaries and creating cutting-edge solutions continues to inspire and shape the future of technological innovation.