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For the Inventor, By the Inventor

Hirakata, Japan

Genshu Fuse

This inventor holds 15 USPTO granted patents. Top assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corporation, Agency of Industrial Science and Technology. Active years: 1984-2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Genshu Fuse. Retrieved from https://idiyas.com/inventor/genshu-fuse

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 11

Forward Citations = 525(Granted Patents)


Location History:

  • Osaka, JP (1991)
  • Toyonaka, JP (1993 - 1995)
  • Hirakata, JP (1984 - 2001)

Company Filing History:

goldMedal12 out of 27,375 
 
Matsushita Electric Industrial Co., Ltd.
 patents
silverMedal2 out of 655 
 
Matsushita Electronics Corporation
 patents
bronzeMedal1 out of 1,430 
 
Agency of Industrial Science and Technology
 patents

Years Active: 1984-2001

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15 patents (USPTO):Explore Patents
1. RE37228 - Method of fabricating semiconductor device (2001-06-12),
2. 5476006 - Crystal evaluation apparatus and crystal evaluation method (1995-12-19),
3. 5466612 - Method of manufacturing a solid-state image pickup device (1995-11-14),
4. 5270227 - Method for fabrication of semiconductor device utilizing ion (1993-12-14),
5. 5270226 - Manufacturing method for LDDFETS using oblique ion implantion technique (1993-12-14),
6. 5223445 - Large angle ion implantation method (1993-06-29),
7. 5057444 - Method of fabricating semiconductor device (1991-10-15),
8. 5049518 - Method of making a trench dram cell (1991-09-17),
9. 5026658 - Method of making a trench capacitor dram cell (1991-06-25),
10. 5013673 - Implantation method for uniform trench sidewall doping by scanning (1991-05-07),
11. 4920390 - Semiconductor memory device and method of fabricating the same (1990-04-24),
12. 4918027 - Method of fabricating semiconductor device (1990-04-17),
13. 4861729 - Method of doping impurities into sidewall of trench by use of plasma (1989-08-29),
14. 4764483 - Method for burying a step in a semiconductor substrate (1988-08-16),
15. 4487635 - Method of fabricating a multi-layer type semiconductor device including (1984-12-11),

Title: Genshu Fuse: Innovator in Semiconductor Technology

Introduction

Genshu Fuse is a prominent inventor based in Hirakata, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 15 patents. His innovative approaches have paved the way for advancements in semiconductor fabrication and evaluation.

Latest Patents

Among his latest patents is a method of fabricating a semiconductor device. This method involves several steps, including forming a trench on a semiconductor substrate and positioning the substrate at different angles to inject ions effectively. Another notable patent is for a crystal evaluation apparatus and method. This invention includes a cell region with an anode and cathode, designed for anodic oxidation and subsequent removal of the oxide film on a semiconductor substrate. The method allows for high-resolution observation of defects and impurity distribution on the substrate.

Career Highlights

Genshu Fuse has worked with notable companies such as Matsushita Electric Industrial Co., Ltd. and Matsushita Electronics Corporation. His experience in these organizations has contributed to his expertise in semiconductor technologies and innovations.

Collaborations

Some of his coworkers include Takashi Ohzone and Toshio Yamada. Their collaboration has likely fostered a creative environment that encourages innovation in semiconductor research.

Conclusion

Genshu Fuse's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the field. His work continues to influence advancements in semiconductor fabrication and evaluation methods.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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