Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Director-general of the Agency of Industrial Science and Technology

Genshu Fuse

Takashi Ohzone

Shinji Odanaka

Toshio Yamada

Masaki Fukumoto

Koichi Kugimiya

Toshiki Yabu

Takashi Hirao

Shuichi Kameyama

Takashi Hori

Ichiro Nakao

Kazumi Kurimoto

Morio Inoue

Kenji Tateiwa

Shigenobu Akiyama

Hideaki Shimoda

Shingi Fujii

Katuya Ishikawa

A method of fabricating a semiconductor device comprising a step of forming a trench selectively on a semiconductor substrate, a step of positioning said semiconductor substrate to a first position inclined to a plane vertical to ion beams, a step of injecting ions by emitting ion beams to a side-wall of the trench of the semiconductor substrate at the first position, a step of positioning said semiconductor substrate to a second position which is different from the first position by rotating it, and a step of injecting ions by emitting ion beams to a side-wall of the trench of the semiconductor substrate at the second position.

Method of fabricating semiconductor device

Crystal evaluation apparatus is disclosed which includes a cell region having an anode and a cathode, a reservoir tank for supplying of an aqueous solution for forming an anodic oxide film in the cell region, a reservoir tank for supplying of an aqueous solution for removing the anodic oxide film and a scanning microprobe microscope having a scanning microprobe, installed inside the cell region. A crystal evaluation method is also disclosed which contains anodic oxidation on a semiconductor substrate, removal of an anodic oxide film developed. The semiconductor substrate is observed with a scanning probe microscope having a scanning microprobe. The oxide film is formed on the semiconductor substrate by the anodic oxidation method and then removed by a mixture of hydrofluoric acid and ammonium fluoride. The anodic oxidation method exerts no or little physical impact on the substrate. The hydrofluoric acid and ammonium fluoride mixture removes selectively only the oxide film so that secondary ion implantation defects are exposed to a surface of the substrate. The shape or configuration of the secondary ion implantation defects is observed with an atomic force microscope having a high resolution on the order of nano meter. Therefore, the shape of the defects on the order of nano meter may be observed. In addition, the distribution of impurity concentration over the surface of the substrate may be measured very accurately.

Crystal evaluation apparatus and crystal evaluation method

A dielectric film is formed on a P type silicon substrate. Then a specified resist pattern is formed on the dielectric film. Using this resist pattern as the mask, a phosphorus ion beam is implanted. Then, removing the resist pattern, heat treatment is given. By this heat treatment, a photo diode is formed in a depth of about 1 .mu.m. A specified resist pattern is formed again on the dielectric film. Using this resist pattern as the mask, boron ions are implanted. Thus, a channel stopper region is formed. Afterwards, removing the resist pattern, the dielectric film is removed. Again, a dielectric film is formed on the silicon substrate. Later, a stacked oxide film is formed in the other regions than the region for forming the photo diode on the dielectric film. Using the stacked oxide film as the mask, a boron ion beam is implanted. When operated in such conditions, a P type diffusion layer of opposite conductive type of photo diode was formed on the surface of the photo diode, and the leak current in the photo diode becomes low. Consecutively, a fluorine ion beam is implanted on the entire surface of the silicon substrate. Thus, on the surface of the photo diode and on the P type diffusion layer, a diffusion layer by fluorine is provided. Thus, to suppress the leak current generated in the photo diode, the interface state density is lowered, while the level of implantation defects may be suppressed at the same time.

Method of manufacturing a solid-state image pickup device

By symmetrically forming source and drain regions to the gate electrodes, electrically symmetrical transistor characteristics are obtained. After forming the first source and drain regions by large-tilt-angle ion implantation, without a sidewall in the gate electrode or after forming a sidewall shorter than the distance in the lateral direction of the second source and drain regions from the end of the mask for ion implantation, the diffusion of the second source and drain regions in the lateral direction is restricted to the maximum extent by heat treatment for a short time, and then the end of the gate electrode and the end of the second source and drain regions are matched, or their overlap region is formed. As a result, the manufacturing method of the MOS transistor results in both high performance and high reliability.

Manufacturing method for LDDFETS using oblique ion implantion technique

An improved method for fabrication of a super-high density semiconductor device wherein ion implantation is used to eliminate defects or inhibit the occurrence of growth of defects in the semiconductor device. Ions of high concentration are implanted into a monocrystal semiconductor region in which principal elements such as bipolar element and MOS element are formed, by using a mask pattern covering the semiconductor region and at a largely inclined implantation angle equal to or of more than 20 degrees. This provides for formation of amorphous regions 170A, 170B extending sufficiently into areas beneath the ends of the mask. The amorphous regions are recrystallized by heat treatment, thereby inhibiting the growth of a corner defect known as 'voids 21' which has often occurred at edges of amorphous regions 170A, 170B in the conventional method. Thus, a device which is less liable to electrical leaks is provided.

Method for fabrication of semiconductor device utilizing ion

An ion implanting method which suppresses defects by changing the shape of the amorphous layer formed by ion injection from that of a conventional device. After forming a mask pattern on a semiconductor wafer, amorphous layers are then formed with sufficient penetration under the mask material by implanting ions at an implant angle greater than or equal to 20 degrees with a dose amount enough for forming amorphous layers. In this large angle ion implanting method, the edge of each amorphous layer becomes dull and, thereby, no voids are formed in a successive heat treatment.

Large angle ion implantation method

A semiconductor memory, particularly, a dynamic RAM, is provided having a two-cell one-contact memory cell connection structure. A connection portion between memory cells in a silicon substrate of a dynamic RAM, wherein each memory cell has one silicon island enclosed by a trench and provided with two transistor cells within said island, is formed by connecting a polysilicon electrode, enclosing the periphery of the silicon island at the inside of the trench and separated at two portions of the periphery of the silicon island, to the source or drain of one of the two transistor cells of the memory cell. The connection of the polysilicon electrode to the source or drain of the transistor cell of each of two adjacent memory cells can be easily achieved through self aligning by using a fine-trench polysilicon burying method or a selective epitaxial method.

Method of making a trench dram cell

Disclosed is a semiconductor memory device (DRAM) which includes a plurality of island regions, at least one cell transistor disposed on each island region and cylindrical capacitor surrounding said each island region. By so composing, the capacity of the cell capacitor incorporated into a small space can be increased. Also disclosed is method of fabricating a semiconductor memory device which includes a step of forming a groove having a necessary depth in a semiconductor substrate, a step of depositing a membrane excelling in coverage on it, a step of etching by an etching method having a strong anisotropy in the vertical direction while leaving said deposit membrane on sidewall, and a step of etching deeper the exposed portion of the semiconductor surface in the groove and forming capacity element and isolation region by using this deep trench.

Method of making a trench capacitor dram cell

An ion implantation method comprising doping a trench sidewall formed in the surface of a semiconductor substrate, with impurities by intermittently rotating step ion implantation carried out in the state that said sidewall is angled with respect to an ion beam, wherein;

Implantation method for uniform trench sidewall doping by scanning

A semiconductor memory device (DRAM) includes a plurality of island regions, at least one cell transistor disposed on each island region and a cylindrical capacitor surrounding each island region. With such a structure, the capacity of the cell capacitor incorporated into a small space can be increased. Furthermore, a method of fabricating a semiconductor memory device includes a step of forming a groove having a necessary depth in a semiconductor substrate, a step of depositing a membrane having excellent covering characteristics in the groove, a step of etching by using an etching method having a strong anisotropy in the vertical direction while leaving the deposited membrane on a sidewall, and a step of etching the exposed portion of the semiconductor surface deeper in the groove and forming a capacity element and isolation region by using this deep trench.

Semiconductor memory device and method of fabricating the same

A method of fabricating a semiconductor device comprising a step of forming a trench on a semiconductor substrate, a step of positioning the semiconductor substrate in a first position such that the direction of the ion beams is inclined to a plane which is perpendicular to the principal surface of the semiconductor substrate and which is parallel to a first side-wall of the trench, a step of implanting ions into the first side-wall by emitting ion beams onto the first side-wall of the trench of the semiconductor substrate at the first position, a step of rotating the semiconductor substrate about an axis perpendicular to the principal surface thereof to a second position which is different from the first position, a step of implanting ions into a second side-wall by emitting ion beams onto the second side-wall of the trench of the semiconductor substrate at the second position, a step of rotating the semiconductor substrate about the axis to a third position which is different from the first and second positions, a step of implanting ions into a third side-wall by emitting ion beams onto the third side-wall of the trench of the semiconductor substrate at the third position, a step of rotating the semiconductor substrate about the axis to a fourth position which is different from the first, second and third positions, and a step of implanting ions into a fourth side-wall by emitting ion beams onto the fourth side-wall of the trench of the semiconductor substrate at the fourth position.

A method in which in order to dope impurities, with excellent controllability, into a sidewall of a trench formed in a semiconductor substrate, plasma is generated in a gas including the impurities and the semiconductor substrate is disposed in or near the plasma, so that the impurities may be doped into the sidewall of the trench uniformly and at high precision of concentration control; wherein one of a duluted B.sub.2 H.sub.6 gas and diluted AsH.sub.3 gas is chosen as the gas of the plasma, whereby one of B and As as the impurities directly enters the sidewall of the trench without first passing through a film.

Method of doping impurities into sidewall of trench by use of plasma

Disclosed is a method for burying a step in a semiconductor substrate in which (1) SiO.sub.2 layer is formed on a lower part of the step, (2) photoresist layer with equal thickness to the height of the step on the SiO.sub.2 layer at a portion corresponding to the lower part of the step, (3) sputter-SiO.sub.2 layer is formed by sputtering on the photoresist layer and SiO.sub.2 layer, (4) another photoresist layer is formed on the sputter-SiO.sub.2 layer, (5) the another photoresist layer and sputter-SiO.sub.2 layer are removed, and (6) the SiO.sub.2 layer and photoresist layer are removed. By this method, semiconductor substrate with flatness of within 50 nm in a 6-inch wafer can be obtained.

Method for burying a step in a semiconductor substrate

A method of producing a superior semiconductor crystallized layer rapidly on a semiconductor substrate with the surface thereof covered with an insulating film is disclosed. An opening, desirably formed by at least two insulating films, is formed at an intersection of scribe lines of the semiconductor substrate. A polycrystal semiconductor film is formed on the insulating films and the opening, after which an energy beam is irradiated spirally on the polycrystal semiconductor film in such a manner that the beam passes at least one opening during each rotation thereof thereby to transform the polycrystal semiconductor film into a crystallized layer for forming a semiconductor element.

Growing community of inventors

Hirakata, Japan

Genshu Fuse