Singapore, Singapore

Gao Feng

This inventor holds 3 USPTO granted patents. Top assignee: Chartered Semiconductor Manufacturing Ltd (Corporation). Active years: 2002-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Gao Feng. Retrieved from https://idiyas.com/inventor/gao-feng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 1.9

ph-index = 3

Forward Citations = 43(Granted Patents)


Company Filing History:


Years Active: 2002-2003

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3 patents (USPTO):Explore Patents

Title: Innovations by Inventor Gao Feng

Introduction

Gao Feng is a notable inventor based in Singapore, SG. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His work focuses on improving the quality and control of gate structures in semiconductor devices.

Latest Patents

Gao Feng's latest patents include a "Method for forming damascene dual gate for improved oxide uniformity and control." This innovative method involves growing layers of gate oxide or gate base materials of varying thicknesses for dual gate structures. The process begins with a semiconductor surface where STI regions have been formed. A layer of gate base material is then grown over this surface. A dielectric, such as nitride, is deposited, masked, and etched to create thin gate base material in specific regions. The gate base material is etched to the desired thickness, resulting in a first thin layer of gate base material. Subsequently, a thick layer of gate electrode material is deposited and polished down to the surface of the dielectric, creating gate electrode structures above thin layers of gate base materials of different thicknesses.

Another significant patent is the "Method of dual gate process," which describes a new technique for forming dual gate dielectrics with high quality. This method allows for separate control of both thin and thick gate dielectric thicknesses. An isolation region separates two active areas in a semiconductor substrate. A first gate dielectric layer is formed over both active areas, followed by the removal of this layer in one area. A second gate dielectric layer, which is nitrided and has a greater electrical thickness, is then formed in the second active area. This process culminates in the formation of first and second gate transistors in their respective active areas.

Career Highlights

Gao Feng is currently employed at Chartered Semiconductor Manufacturing Ltd, where he continues to innovate in semiconductor technology. His work has been instrumental in advancing the capabilities of semiconductor devices, particularly in the area of gate structures.

Collaborations

Gao Feng has collaborated with notable colleagues such as Yong Meng Lee and Ravi Sundaresan. Their combined expertise has contributed to the successful development of innovative semiconductor technologies.

Conclusion

Gao Feng's contributions to semiconductor technology through his patents and collaborations highlight his role as a significant inventor in the field. His innovative methods for improving gate structures are paving the way for advancements in semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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