Chartered Semiconductor Manufacturing Ltd (corporation)

Gao Feng

Yong Meng Lee

Ravi Sundaresan

Yunqzang Zhang

Li Xia

A method to grow layers of gate oxide or gate base materials of different thicknesses for dual gate structures. The process starts with a semiconductor surface in which STI regions have been formed and over the surface of which a layer of gate base material has been grown. A dielectric, such as nitride, is deposited, masked and etched over a first region where thin gate base material must be created thereby exposing the surface of the deposited layer of gate base material in that region. The gate base material is etched to the desired thickness, creating a first thin layer of gate base material. A thick first layer of gate electrode material, poly, is deposited over the dielectric thereby including the surface of the first thin layer of gate base material, and polished down to the surface of the dielectric leaving gate electrode material deposited in the opening above the first thin layer of gate base material. The process creates over a second region of the gate base material a gate electrode having a second thickness of the gate base material. The dielectric is removed leaving gate electrode structures in place above thin layers of gate base materials, the latter being of different thicknesses.

Method for forming damascene dual gate for improved oxide uniformity and control

A new method for forming dual gate dielectrics having high quality where both thin and thick gate dielectric thicknesses can be controlled separately is described. An isolation region separates a first active area from a second active area in a semiconductor substrate. A first gate dielectric layer is formed overlying the semiconductor substrate in the first and second active areas wherein the first gate dielectric layer has a first electrical thickness. The first gate dielectric layer in the second active area is removed. A second gate dielectric layer is formed in the second active area wherein the second gate dielectric layer has a second electrical thickness greater than the first electrical thickness and wherein the second gate dielectric layer is nitrided. A polysilicon layer is deposited overlying the first and second gate dieectric layers. The layers are patterned to form a first gate transistor in the first active area having the first gate dielectric layer thereunder and to form a second gate transistor in the second active area having the second gate dielectric layer thereunder.

Method of dual gate process

A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H -rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H -rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H -rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.

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Singapore, Singapore

Gao Feng