The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2002
Filed:
Jan. 18, 2000
Yong Meng Lee, Singapore, SG;
Gao Feng, Singapore, SG;
Yunqzang Zhang, Singapore, SG;
Ravi Sundaresan, Plano, TX (US);
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H -rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H -rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H -rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.