logo

For the Inventor, By the Inventor

Saratoga, CA, United States of America

Fu Chiung Chong

This inventor holds 24 USPTO granted patents and 4 published patent applications, primarily in High Density Interconnects. Top assignees: Nanonexus Corporation, Verigy (Singapore) Pte. Ltd., Advantest (Singapore) Pte Ltd. Active years: 1999-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fu Chiung Chong. Retrieved from https://idiyas.com/inventor/fu-chiung-chong

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 24 

% Patents Active = 8.3

Average Co-Inventor Count = 2.7

ph-index = 15

Forward Citations = 961(Granted Patents)


Company Filing History:

goldMedal18 out of 19 
 
Nanonexus Corporation
 patents
silverMedal4 out of 115 
 
Verigy (Singapore) Pte. Ltd.
 patents
bronzeMedal1 out of 35 
 
Advantest (Singapore) Pte Ltd
 patents
4. 1 out of 234 
 
Kulicke and Soffa Industries, Inc.
 patents

Years Active: 1999-2013

Loading Chart...
Areas of Expertise:
Probe Card Assemblies
High Density Interconnects
Integrated Circuits
Testing Systems
Manufacturing Processes
Electronic Circuit
Wafer Level Springs
Massively Parallel Interface
Stress Metal Spring
Miniaturized Contact Spring
Fabrication Cycle
Compliant Probe Card
24 patents (USPTO):Explore Patents
1. 8575954 - Structures and processes for fabrication of probe card assemblies with multi-layer interconnect (2013-11-05),
2. 7952373 - Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies (2011-05-31),
3. 7884634 - High density interconnect system having rapid fabrication cycle (2011-02-08),
4. 7872482 - High density interconnect system having rapid fabrication cycle (2011-01-18),
5. 7812626 - High density interconnect system for IC packages and interconnect assemblies (2010-10-12),
6. 7772860 - Massively parallel interface for electronic circuit (2010-08-10),
7. 7621761 - Systems for testing and packaging integrated circuits (2009-11-24),
8. 7579848 - High density interconnect system for IC packages and interconnect assemblies (2009-08-25),
9. 7403029 - Massively parallel interface for electronic circuit (2008-07-22),
10. 7382142 - High density interconnect system having rapid fabrication cycle (2008-06-03),
11. 7349223 - Enhanced compliant probe card systems having improved planarity (2008-03-25),
12. 7247035 - Enhanced stress metal spring contactor (2007-07-24),
13. 7138818 - Massively parallel interface for electronic circuit (2006-11-21),
14. 7137830 - Miniaturized contact spring (2006-11-21),
15. 7126358 - Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies (2006-10-24),

Title: Fu Chiung Chong - Pioneering Inventor from Saratoga

Introduction: Fu Chiung Chong is a renowned inventor based in Saratoga, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Fu Chiung Chong holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his commitment to pushing the boundaries of technological advancement.

Career Highlights: With a career spanning over two decades, Fu Chiung Chong has worked with leading tech companies, research institutions, and universities to develop cutting-edge solutions that have revolutionized various industries.

Collaborations: Throughout his career, Fu Chiung Chong has collaborated with top engineers, scientists, and researchers, fostering a culture of innovation and creativity that has led to numerous successful projects and inventions.

Conclusion: Fu Chiung Chong's passion for innovation and his relentless pursuit of excellence have solidified his reputation as a trailblazer in the world of technology, inspiring the next generation of inventors to push the limits of what is possible.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…