The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2008

Filed:

May. 18, 2005
Applicants:

Fu Chiung Chong, Saratoga, CA (US);

Andrew Kao, Fremont, CA (US);

Douglas Mckay, San Jose, CA (US);

Anna Litza, Cupertino, CA (US);

Douglas Modlin, Palo Alto, CA (US);

Sammy Mok, Cupertino, CA (US);

Nitin Parekh, Los Altos, CA (US);

Frank John Swiatowiec, San Jose, CA (US);

Zhaohui Shan, San Jose, CA (US);

Inventors:

Fu Chiung Chong, Saratoga, CA (US);

Andrew Kao, Fremont, CA (US);

Douglas McKay, San Jose, CA (US);

Anna Litza, Cupertino, CA (US);

Douglas Modlin, Palo Alto, CA (US);

Sammy Mok, Cupertino, CA (US);

Nitin Parekh, Los Altos, CA (US);

Frank John Swiatowiec, San Jose, CA (US);

Zhaohui Shan, San Jose, CA (US);

Assignee:

NanoNexus, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.


Find Patent Forward Citations

Loading…