Erich Franz Haratsch

This inventor holds 211 USPTO granted patents and 13 published patent applications and 9 EPO patents, primarily in Solid-State Drives (CPC class G11C11-5642). Top assignees: Seagate Technology Incorporated, Lsi Corporation, Agere Systems Inc.. Active years: 2004-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Erich Franz Haratsch. Retrieved from https://idiyas.com/inventor/erich-franz-haratsch

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 211 (Patent Applications = 13)

% Patents Active = 72.0

EPO Patents = 9 (Patent Applications = 11)

Average Co-Inventor Count = 2.9

ph-index = 17

Forward Citations = 1,661(Granted Patents)

Forward Citations (Not Self Cited) = 1,537(Dec 10, 2025)

Inventors with similar research interests:

🔬 See more inventors

Location History:

Bradley Beach, NJ (US) (2004 - 2012)
Allentown, PA (US) (2014)
San Jose, CA (2016)
Bethelhem, PA (US) (2018)
Bethlehem, PA (US) (2006 - 2019)
Fremont, CA (US) (2019)
San Jose, CA (US) (2015 - 2023)
Palo Alto, CA (US) (2022 - 2023)

Company Filing History:

140 out of 8,750

Seagate Technology Incorporated

Alcatel-Lucent USA Inc.

patents

5. 1 out of 1,813

Avago Technologies General IP (Singapore) Pte. Ltd.

patents

6. 1 out of 9,364

Lucent Technologies Inc.

patents

7. 1 out of 834,570

Other

patents

Years Active: 2004-2023

Loading Chart...

Areas of Expertise:

SSD Performance

Error Mitigation

Data Compression

Read Thresholds

Memory Cells

NAND Memory

Decoding Errors

Storage Devices

Adaptive Read Retry

Latency Management

Data Deduplication

Flash Memories

211 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11614865 - Controlling SSD performance by the number of active memory dies (2023-03-28),

2. 11595058 - Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells (2023-02-28),

3. 11545230 - Manufacturer self-test for solid-state drives (2023-01-03),

4. 11500547 - Mitigating data errors in a storage device (2022-11-15),

5. 11443826 - Storage area retirement in a storage device (2022-09-13),

6. 11430529 - Capacitance coupling parameter estimation in flash memories (2022-08-30),

7. 11349495 - Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells (2022-05-31),

8. 11347394 - Controlling SSD performance by the number of active memory dies (2022-05-31),

9. 11307997 - Logical to physical data storage mapping (2022-04-19),

10. 11307806 - Controlling SSD performance by queue depth (2022-04-19),

11. 11139833 - Adaptive read retry optimization (2021-10-05),

12. 11133831 - Code rate adaptation (2021-09-28),

13. 11132244 - Block health checking (2021-09-28),

14. 11042316 - Reordered data deduplication in storage devices (2021-06-22),

15. 11024396 - Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory (2021-06-01),

Title: Erich Franz Haratsch: Innovating the Future of Solid State Devices

Introduction:

Erich Franz Haratsch, a prominent inventor based in San Jose, CA, has made significant contributions to the field of solid-state devices (SSDs). With an impressive portfolio of 210 patents, Haratsch has consistently strived to improve the performance and reliability of SSDs. This article explores some of his latest patents, career highlights, and collaborations in the industry.

Latest Patents:

One of Haratsch's recent patents revolves around controlling SSD performance by regulating the depth of the request queue. This innovative approach enhances the performance of SSDs by monitoring the request queue, determining the number of active memory dies, and strategically delaying requests to optimize performance.

Additionally, Haratsch has patented a method for recovering from hard decoding errors in NAND memory cells. By remapping log likelihood ratio (LLR) values, the unsuccessful decoding of codeword bits in NAND memory cells can be mitigated. Haratsch's approach includes estimating error rates and utilizing single-level cell (SLC) reading to identify and adaptively change the LLR mapping.

Career Highlights:

Throughout his career, Haratsch has demonstrated a keen focus on storage technology. He has held positions at renowned companies such as Seagate Technology and LSI Corporation. These roles have allowed him to contribute to cutting-edge projects and lead innovation in the storage industry.

Collaborations:

Partnerships and collaborations have played a pivotal role in Haratsch's career. He has worked alongside notable industry professionals, including Yunxiang Wu and Zhengang Chen. Collaborating with such talented individuals has further propelled Haratsch's creativity and facilitated the development of groundbreaking SSD technologies.

Conclusion:

Erich Franz Haratsch's multitude of patents exhibits his passion for pushing the boundaries of SSD performance and reliability. His pioneering work in controlling SSD performance and recovering from decoding errors showcases his dedication to revolutionizing the field. Haratsch's extensive experience in prominent companies, as well as his successful collaborations, solidify his status as a leading innovator in the realm of solid-state devices.

Profile summary based on public USPTO records.