The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2023
Filed:
Apr. 29, 2022
Applicant:
Seagate Technology Llc, Fremont, CA (US);
Inventors:
Naveen Kumar, San Jose, CA (US);
Shuhei Tanakamaru, San Jose, CA (US);
Erich Franz Haratsch, San Jose, CA (US);
Assignee:
Seagate Technology LLC, Fremont, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/01 (2006.01); H03M 13/11 (2006.01); H03M 13/39 (2006.01);
U.S. Cl.
CPC ...
H03M 13/015 (2013.01); H03M 13/1105 (2013.01); H03M 13/1177 (2013.01); H03M 13/3927 (2013.01);
Abstract
Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.