Seagate Technology Incorporated

Lsi Corporation

Agere Systems Inc.

Other

Lucent Technologies Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Alcatel-lucent USA Inc.

Erich Franz Haratsch

Yunxiang Wu

Zhengang Chen

Abdelhakim Alhussien

Sundararajan Sankaranarayanan

Yu Cai

Earl T Cohen

Andrei Vityaev

Johnson Yen

Ludovic Danjean

Victor A Krachkovsky

Milos Ivkovic

Kameran Azadet

Nenad Miladinovic

George Mathew

Ning Chen

Ming Jin

Kelly K Fitzpatrick

Jongseung Park

Jeremy Werner

Shuhei Tanakamaru

Abdel-Hakim S Alhussien

Shaohua Yang

Ivana Djurdjevic

Clifton James Williamson

Hongmei Xie

Jonathan James Ashley

AbdelHakim S Alhussien

Harley F Burger, Jr

Abdel Hakim S Alhussien

Fan Zhang

Leonid Baryudin

Nils Graef

Yue Li

Dana Lynn Simonson

Alex G Tang

Kurt J Worrell

Bruce Alexander Wilson

Zongwang Li

Nayak Ratnakar Aravind

Timothy B Lund

David Patmore

Yingji Ju

Thuy Van Nguyen

Abdel Hakim Alhussien

Naveen Kumar

Yingquan Wu

Yuan Xing Lee

Stephen D Hanna

Jun Xiao

Carl E Forhan

James Arthur Bailey

Timothy W Swatosh

Seongwook Jeong

Meysam Asadi

Scott McClure

Zhimin Dong

Ara Patapoutian

Ryan James Goss

Harish Viswanathan

Jamal Riani

Jeffrey Paul Grundvig

Timothy Lawrence Canepa

Wu Chang

Gordon James Coleman

David Scott Ebsen

Changyou Xu

Andrew John Blanksby

Robert H Leonowich

Scott M Dziak

Zheng Wang

Jefferson E Singleton

Jason S Goldberg

Ruwan Ratnayake

David G Springberg

Ying Quan Wu

Kripa Venkatachalam

Alex Ga Hing Tang

Ludovik Danjean

Adbel Hakim S Alhussien

Abdelhakim S Alhussein

Bijan Eskandari-Gharnin

Zejiang Qu

Hackbin Kim

Steven Howe

Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Controlling SSD performance by the number of active memory dies

Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells

An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.

Manufacturer self-test for solid-state drives

Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.

Mitigating data errors in a storage device

Systems and methods presented herein provide for testing degradation in a storage device. In one embodiment, a storage controller is operable to test individual portions of a first of the plurality of storage areas of the storage device by: analyzing individual portions of the first storage area; determining that one or more of the individual portions of the first storage area have failed; and retire the failed one or more portions of the first storage area. The storage controller is further operable to write to the first storage area using an error correction code (ECC), and to test the remaining portions of the first storage area to determine whether the first storage area should be retired in response to writing to the first storage area.

Storage area retirement in a storage device

A method for capacitance coupling parameter estimation includes determining a plurality of mean voltages among a plurality of memory cells of the memory in each of a plurality of cases related to inter-cell interference, generating a plurality of middle state mean voltages in response to the mean voltages, and adjusting one or more threshold voltages used to read from the memory based on the middle state mean voltages to operate independently of knowledge of middle state distributions in the memory cells.

Capacitance coupling parameter estimation in flash memories

Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a queue depth for the request queue, determining a target interval based on the queue depth and a target queue depth, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Controlling SSD performance by queue depth

Systems, methods and computer-readable memory for garbage collection in a storage device. One method comprises, upon a write of data to a first garbage collection unit (GCU) of the storage device, incrementing a number of logical mapping units stored in the first GCU along with a number of logical mapping units with valid data stored in the first GCU. A number of logical mapping units with invalid data stored in a second GCU is decremented based on the incremented number of logical mapping units with valid data stored in the first GCU. The second GCU is erased when a valid data rate of the second GCU is below a valid data rate of the first GCU.

Logical to physical data storage mapping

Systems, devices, and methods are presented that allow a data channel to adaptively vary a change in a reference voltage used to read data from a solid state memory. The change in the reference voltage may be determined based on a measured error statistic of the solid state memory. A hard decision low density parity check (HLDPC) decoder may be utilized in conjunction with a soft decision low density parity check (SLDPC).

Adaptive read retry optimization

A method includes determining a portion of a block of a storage device to read after programming, and reading the portion of the block and determining a maximum error count for the portion of the block. The maximum error count is compared to a threshold. When the maximum error count exceeds the threshold, a code rate of an error correction coding used to program the block is adjusted, or a code rate test is performed on the entire block.

Block health checking

A method includes programming data in a block of a storage device, and reading back the programmed data and determining a maximum error count for the block. A code rate index that satisfies correction of the maximum error count for the block is determined. A current code rate index is adjusted to the code rate index that satisfies correction of the maximum error count for the block.

Code rate adaptation

A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.

Reordered data deduplication in storage devices

Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.

Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory

Growing community of inventors

San Jose, CA, United States of America

Erich Franz Haratsch