Tigard, OR, United States of America

Eric G Webb

This inventor holds 23 USPTO granted patents and 4 published patent applications, primarily in Semiconductor Processing. Top assignee: Novellus Systems Incorporated. Active years: 2003-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Eric G Webb. Retrieved from https://idiyas.com/inventor/eric-g-webb

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 23 

% Patents Active = 56.5

Average Co-Inventor Count = 4.3

ph-index = 12

Forward Citations = 323(Granted Patents)


Location History:

  • Salem, OR (US) (2003 - 2011)
  • West Linn, OR (US) (2009 - 2013)
  • Tigard, OR (US) (2011 - 2013)
  • Camas, WA (US) (2015)
  • Camas, OR (US) (2016)

Company Filing History:


Years Active: 2003-2016

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Areas of Expertise:
Wet Etching
Copper Removal
Planarization
Electroplating
Photoresist-Free
Interconnect Structure
Electroless Plating
Deposit Morphology
Barrier Layer
Topography Reduction
Defect Reduction
Ruthenium Seed Layer
23 patents (USPTO):Explore Patents

Title: Innovations by Eric G Webb: Pioneering Wet Etching Methods in Semiconductor Processing

Introduction: Eric G Webb, a prominent inventor based in Tigard, Oregon, has made substantial contributions to the field of semiconductor processing. With a remarkable portfolio of 23 patents to his name, Webb's latest innovations reflect his expertise and dedication to advancing technology in this critical sector.

Latest Patents: One of Webb's noteworthy patents is focused on wet etching methods for copper removal and planarization in semiconductor processing. This innovative technique employs a wet etching solution comprising complexing agents, such as bidentate, tridentate, and quadridentate agents, combined with an oxidizer. The solutions operate at a pH between 5 and 12 and allow for efficient etching of exposed copper regions on semiconductor substrates. Notably, the process is designed to be substantially isotropic, minimizing the formation of insoluble species on copper surfaces, and finds utility in various semiconductor fabrication processes, including the removal of copper overburden and planarization of copper surfaces.

Career Highlights: Eric G Webb's career has been marked by his extensive work with Novellus Systems Incorporated, where he has played a pivotal role in developing innovative semiconductor manufacturing solutions. His patents have not only highlighted his technical acumen but have also significantly impacted the efficiency and effectiveness of semiconductor fabrication techniques.

Collaborations: Webb collaborates with talented coworkers, including Steven T Mayer and Jonathan David Reid. Their teamwork brings together a wealth of expertise and creativity, leading to the development of cutting-edge technologies in semiconductor processing.

Conclusion: Eric G Webb's contributions to the field of semiconductor processing through his patents underscore his role as a leading innovator. With a focus on enhancing manufacturing processes, his work continues to shape the landscape of advanced technology in the semiconductor industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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