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For the Inventor, By the Inventor

Tigard, OR, United States of America

Eric G Webb

USPTO Granted Patents = 23 

Average Co-Inventor Count = 4.3

ph-index = 12

Forward Citations = 321(Granted Patents)


Location History:

  • Salem, OR (US) (2003 - 2011)
  • West Linn, OR (US) (2009 - 2013)
  • Tigard, OR (US) (2011 - 2013)
  • Camas, WA (US) (2015)
  • Camas, OR (US) (2016)

Company Filing History:

goldMedal23 out of 993 
 
Novellus Systems Incorporated
 patents

Years Active: 2003-2016

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23 patents (USPTO):
1. 9447505 - Wet etching methods for copper removal and planarization in semiconductor processing (2016-09-20),
2. 9074286 - Wet etching methods for copper removal and planarization in semiconductor processing (2015-07-07),
3. 8500985 - Photoresist-free metal deposition (2013-08-06),
4. 8481432 - Fabrication of semiconductor interconnect structure (2013-07-09),
5. 8470191 - Topography reduction and control by selective accelerator removal (2013-06-25),
6. 8415261 - Capping before barrier-removal IC fabrication method (2013-04-09),
7. 8372757 - Wet etching methods for copper removal and planarization in semiconductor processing (2013-02-12),
8. 8257781 - Electroless plating-liquid system (2012-09-04),
9. 8197662 - Deposit morphology of electroplated copper (2012-06-12),
10. 8158532 - Topography reduction and control by selective accelerator removal (2012-04-17),
11. 8043958 - Capping before barrier-removal IC fabrication method (2011-10-25),
12. 7972970 - Fabrication of semiconductor interconnect structure (2011-07-05),
13. 7947163 - Photoresist-free metal deposition (2011-05-24),
14. 7897198 - Electroless layer plating process and apparatus (2011-03-01),
15. 7879218 - Deposit morphology of electroplated copper (2011-02-01),

Title: Innovations by Eric G Webb: Pioneering Wet Etching Methods in Semiconductor Processing

Introduction: Eric G Webb, a prominent inventor based in Tigard, Oregon, has made substantial contributions to the field of semiconductor processing. With a remarkable portfolio of 23 patents to his name, Webb's latest innovations reflect his expertise and dedication to advancing technology in this critical sector.

Latest Patents: One of Webb's noteworthy patents is focused on wet etching methods for copper removal and planarization in semiconductor processing. This innovative technique employs a wet etching solution comprising complexing agents, such as bidentate, tridentate, and quadridentate agents, combined with an oxidizer. The solutions operate at a pH between 5 and 12 and allow for efficient etching of exposed copper regions on semiconductor substrates. Notably, the process is designed to be substantially isotropic, minimizing the formation of insoluble species on copper surfaces, and finds utility in various semiconductor fabrication processes, including the removal of copper overburden and planarization of copper surfaces.

Career Highlights: Eric G Webb's career has been marked by his extensive work with Novellus Systems Incorporated, where he has played a pivotal role in developing innovative semiconductor manufacturing solutions. His patents have not only highlighted his technical acumen but have also significantly impacted the efficiency and effectiveness of semiconductor fabrication techniques.

Collaborations: Webb collaborates with talented coworkers, including Steven T Mayer and Jonathan David Reid. Their teamwork brings together a wealth of expertise and creativity, leading to the development of cutting-edge technologies in semiconductor processing.

Conclusion: Eric G Webb's contributions to the field of semiconductor processing through his patents underscore his role as a leading innovator. With a focus on enhancing manufacturing processes, his work continues to shape the landscape of advanced technology in the semiconductor industry.

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